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INTEGRATED CIRCUITS
DATA SHEET
P8xCx70 family Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
Product specification Supersedes data of 1999 May 17 File under Integrated Circuits, IC20 1999 Jun 11
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
CONTENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION MEMORY ORGANIZATION I/O FACILITY WATCHDOG TIMER (T3) REDUCED POWER MODES I2C-BUS SERIAL I/O INTERRUPT SYSTEM OSCILLATOR CIRCUITRY RESET PIN FUNCTION SELECTION 7-BIT PWM DAC AFT INPUTS (ADC) DATA SLICER AND CC COMMAND INTERPRETER CC/OSD DISPLAY FUNCTION MEMORY DATA BIT ALLOCATION PROGRAMMER LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION RELEASE LETTER OF ERRATA PACKAGE OUTLINE SOLDERING DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
P8xCx70 family
1999 Jun 11
2
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
1 FEATURES
P8xCx70 family
* Fully static 80C51 CPU * 64-kbyte programmable ROM * 1-kbyte RAM * On-chip 12 MHz crystal oscillator * Eight 7-bit PWM outputs for analog controls * Three input 4-bit software Analog-to-Digital Converters (ADC) * Power-on reset and Watchdog Timer * 29 I/O lines via individual addressable controls * Eight port lines (Port 2) with 10 mA LED sink (<1 V) capability * On-Screen Display (OSD) and Closed Caption (CC) with V-chip function * Byte-level I2C-bus interface up to 400 kHz * Three power reduction modes: Standby, Idle and Power-down * Power supply: 5.0 V 10% * Operating temperature: -20 to +70 C * 52-pin shrink dual in-line package (SDIP52). 2 GENERAL DESCRIPTION
The P8xCx70 family consists of the following devices: * P83C270 * P83C370 * P83C570 * P83C770 * P87C770. The term P8xCx70 is used throughout this data sheet to refer to all family members; differences between devices are highlighted in the text. The P8xCx70 family of microcontrollers are 8-bit, 80C51-based microcontrollers specifically designed for the NTSC TV market. Each device has an On-Screen Display, control functions and Closed Caption that extracts, decodes (software) and displays caption signals from NTSC TV signals. Extended Data Service (XDS) is via the software command interpreter and the V-chip is also implemented.
3
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME P83C270AAR P83C370AAR P83C570AAR P83C770AAR P87C770AAR SDIP52 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) VERSION SOT247-1 24-kbyte 32-kbyte 48-kbyte 64-kbyte 64-kbyte (OTP) 512-byte 512-byte 1-kbyte 1-kbyte 1-kbyte ROM RAM
1999 Jun 11
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book, full pagewidth
1999 Jun 11
VDDA VSSD VDDP VSSA VDDC XI TWO 16-BIT TIMER/ COUNTERS (T0 AND T1) CPU ALE/PROG 8-BIT WATCHDOG TIMER (T3) ROM 64-KBYTES XO RESET PSEN VPP/EA 80C51 CORE EXCLUDING ROM/RAM PARALLEL I/O PORT FUNCTION COMBINED PARALLEL I/O PORTS
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Philips Semiconductors
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
BLOCK DIAGRAM
R FB G
B
VSYNC HSYNC
AFT0(2) AFT2(2) AFT1(2)
RAM 1-KBYTE
ON-SCREEN DISPLAY (OSD)
3 x 4-BIT ADCS
8-bit internal bus
4
9 x 7-BIT DACS
CC DATA SLICER
I2C-BUS INTERFACE
2
8
8
5
8 REFH IREF CVBS SDA(3) SCL(3)
MGR380
external interrupts
P2
P0
P1
P3
PWM0 to PWM8(1)
STN
BLK
P8xCx70 family
Product specification
(1) Alternative functions of Port 0 except PWM0 which is an alternative function of Port 1. (2) Alternative functions of Port 1. (3) Alternative functions of Port 3.
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
5 5.1 PINNING INFORMATION Pinning
P8xCx70 family
handbook, halfpage
P0.0/PWM8 P0.1/PWM7 P0.2/PWM6 P0.3/PWM5 P0.4/PWM4 P0.5/PWM3 P0.6/PWM2 P0.7/PWM1 P1.0/AFT0
1 2 3 4 5 6 7 8 9
52 P3.7 51 P3.6 50 P3.5/SDA 49 P3.4/SCL 48 P3.3/T1 47 P3.2/INT0 46 P3.1/T0 45 P3.0/INT1 44 VDDC 43 RESET 42 XI
P1.1/AFT1 10 P1.2/AFT2 11 P1.3/PWM0 12 VSSD 13 P2.7 14 P2.6 15 P2.5 16 P2.4 17 P2.3 18 P2.2 19 P2.1 20 P2.0 21 VSSA 22 CVBS 23 STN 24 BLK 25 IREF 26
MGR372
P83C270 P83C370 P83C570 P83C770 P87C770
41 XO 40 VSSD 39 VDDP 38 VDDA 37 VSYNC 36 HSYNC 35 FB 34 R 33 G 32 B 31 REFH 30 P1.4 29 ALE/PROG 28 VPP/EA 27 PSEN
Fig.2 Pinning configuration.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
5.2 Pin description SDIP52 package PIN 1 to 8 9 10 11 12 13 14 to 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O - I/O - I I I I O I I/O I/O I O O O O I I - - I O I I - I/O I/O I/O I/O DESCRIPTION
P8xCx70 family
Table 1
SYMBOL P0.0/PWM8 to P0.7/PWM1 P1.0/AFT0 P1.1/AFT1 P1.2/AFT2 P1.3/PWM0 VSSD P2.7 to P2.0 VSSA CVBS STN BLK IREF PSEN VPP/EA ALE/PROG P1.4 REFH B G R FB HSYNC VSYNC VDDA VDDP VSSD XO XI RESET VDDC P3.0/INT1 P3.1/T0 P3.2/INT0 P3.3/T1
Port 0 lines P0.0 to P0.7 (open-drain, bidirectional); alternative functions 7-bit PWM outputs. Port 1 line P1.0; alternative function as 4-bit AFT0 input. Port 1 line P1.1; alternative function as 4-bit AFT1 input. Port 1 line P1.2; alternative function as 4-bit AFT2 input. Port 1 I/O line P1.3 (open-drain, bidirectional); alternative function as 7-bit PWM0 output. Ground line for digital circuits. Port 2 lines P2.7 to P2.0 (open-drain, bidirectional). Ground line for analog circuits. Composite video input. Data Slicer decoupling capacitor input, connect to VSSA via a 100 nF capacitor. CVBS signal black level reference, connect to VSSA via a 100 nF capacitor. CVBS signal reference current input, connect to VSSA via a 27 k resistor. Program Store Enable (active LOW); bonded out for testing purpose only. External Access (active LOW); bonded out for testing purpose only. This pin is also used for the 12.75 V programming voltage supply in OTP programming modes. Address Latch Enable; bonded out for testing purpose only. This pin is also used for programming pulses input in OTP programming modes. Port 1 line P1.4 (open-drain, bidirectional). Data Slicer reference high capacitor input, connect to VSSA via a 100 nF capacitor. CC/OSD Blue colour current output. CC/OSD Green colour current output. CC/OSD Red colour current output. CC/OSD fast blanking output. TV horizontal sync input (for OSD synchronization). TV vertical sync input (for OSD synchronization). +5 V analog power supply. +5 V digital power supply for peripherals. Ground line for digital circuits. System oscillator crystal output. System oscillator crystal input. Reset input (active HIGH). +5 V digital power supply for CPU core. Port 3 line P3.0; alternative function as external interrupt 1 input. Port 3 line P3.1; alternative function as Counter 0 input. Port 3 line P3.2; alternative function as external interrupt 0 input. Port 3 line P3.3; alternative function as Counter 1 input.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
SYMBOL P3.4/SCL P3.5/SDA P3.6 P3.7 PIN 49 50 51 52 I/O I/O I/O I/O I/O DESCRIPTION
P8xCx70 family
Port 3 line P3.4 (open-drain, bidirectional); alternative function as I2C-bus clock line (open-drain). Port 3 line P3.5 (open-drain, bidirectional); alternative function as I2C-bus data line (open-drain). Port 3 line P3.6 (open-drain, bidirectional). Port 3 line P3.7 (open-drain, bidirectional).
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Philips Semiconductors
6
MEMORY ORGANIZATION
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
The P8xCx70 family offers a choice of different RAM and ROM configurations; see "Ordering information". The device has no external memory capability, consequently the RD (read) and WR (write) signals are not bonded out. EA (External Access), PSEN (Program Store Enable) and ALE (Address Latch Enable) are bonded out for testing purposes only. For the complete memory map of the P8xC770 family refer to the 80C51 architecture in "Data Handbook IC20". 6.1 SFR address map summary
The SFRs are presented in ascending address order. Table 2 SFR address map summary REGISTER NAME P0 (latch) Stack Pointer (SP) PWM0 (7-bit PWM) Power Control Register (PCON) Timer/Counter Control Register (TCON) Timer/Counter Mode Control Register (TMOD) Timer 0 Low byte (TL0) Timer 1 Low byte (TL1) Timer 0 High byte (TH0) Timer 1 High byte (TH1) P1 (latch) Standby Control Register (STBCON) PWM1 (7-bit PWM) Interrupt Request Register 1 (IRQ1) P2 (latch) PWM2 (7-bit PWM) Interrupt Enable Register 0 (IEN0) P3 (latch) PWM3 (7-bit PWM) Slice Line Register (SL) Interrupt Priority Register 0 (IP0) PWM4 (7-bit PWM) 7 P07 SP7 - TF1 Gate TL07 TL17 TH07 TH17 P17 - - P27 EA P37 - - 6 P06 SP6 - TR1 C/T TL06 TL16 TH06 TH16 P16 - RCC P26 - P36 - - 5 P05 SP5 data5 - TF0 M1 TL05 TL15 TH05 TH15 P15 - data5 RBUSY P25 data5 ES1 P35 data5 - PS1 data5 4 P04 SP4 data4 WLE TR0 M0 TL04 TL14 TH04 TH14 P14 - data4 - P24 data4 - P34 data4 CS4 - data4 3 P03 SP3 data3 GF1 IE1 Gate TL03 TL13 TH03 TH13 P13 - data3 - P23 data3 ET1 P33 data3 CS3 PT1 data3 2 P02 SP2 data2 GF0 IT1 C/T TL02 TL12 TH02 TH12 P12 - data2 - P22 data2 EX1 P32 data2 CS2 PX1 data2 1 P01 SP1 data1 PD IE0 M1 TL01 TL11 TH01 TH11 P11 - data1 - P21 data1 ET0 P31 data1 CS1 PT0 data1 0 P00 SP0 data0 IDL IT0 M0 TL00 TL10 TH00 TH10 P10 STBY data0 - P20 data0 EX0 P30 data0 CS0 PX0 data0
ADDRESS 80H(1) 81H(1) 86H 87H(1) 88H(1) 89H(1) 8AH(1) 8BH(1) 8CH(1) 8DH(1) 90H(1) 92H 96H 98H A0H(1) A6H A8H(1) B0H(1) B6H B7H B8H(1) C6H
PWM0E data6
PWM1E data6
PWM2E data6
P8xCx70 family
Product specification
PWM3E data6
PWM4E data6
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Philips Semiconductors
ADDRESS D0H(1) D6H D7H D8H D9H(2) DAH DBH E0H E6H E7H E8H(1) EAH EBH F0H(1) F4H F5H F6H F8H FFH Notes 1. Standard 80C51 registers. 2. Read only registers.
REGISTER NAME Program Status Word (PSW) PWM5 (7-bit PWM) Closed Caption Data 1 (CCData1) Serial Control Register (S1CON) Status Register (S1STA) Data Shift Register (S1DAT) Slave Address Register (S1ADR) Accumulator (ACC) PWM6 (7-bit PWM) Closed Caption Data 2 (CCData2) Interrupt Enable Register 1 (IEN1) AFT Control Register (AFCON) Busy Interrupt and Watchdog Control Register (BWC) B Register (B) Port 1 Selection Register (P1SEL) PWM8(7-bit PWM) PWM7(7-bit PWM) Interrupt Priority Register 1 (IP1) Watchdog Timer Register (WDT) CY D7
7 AC D6
6 F0
5 data5 D5 STA SC2 D5 SLA4 ACC5 data5 D5 EBUSY AFTH0 - B5 - data5 data5 PBUSY data5
4 RS1 data4 D4 STO SC1 D4 SLA3 ACC4 data4 D4 - AFTL3 - B4 I2CE data4 data4 - data4
3 RS0 data3 D3 SI SC0 D3 SLA2 ACC3 data3 D3 - AFTL2 - B3 - data3 data3 - data3 OV
2 - data2 D2 AA 0 D2 SLA1 ACC2 data2 D2 - AFTL1 - B2 AFT2E data2 data2 - data2
1 P data1 D1 CR1 0 D1 SLA0 ACC1 data1 D1 - AFTL0 EW B1 AFT1E data1 data1 - data1
0 data0 D0 CR0 0 D0 GC ACC0 data0 D0 - AFTC BUSY B0 AFT0E data0 data0 - data0
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
PWM5E data6 CR2 SC4 D7 SLA6 ACC7 D7 - - - B7 - ENS1 SC3 D6 SLA5 ACC6 D6 ECC AFTH1 - B6 -
PWM6E data6
PWM8E data6 PWM7E data6 - data7 PCC data6
P8xCx70 family
Product specification
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
6.2 Display control registers map
P8xCx70 family
The display control registers can only be addressed using MOVX instructions. Table 3 Display control register map REGISTER NAME Display Control Text Vertical Position Text Horizontal Position Fringing Control Text Area End Scroll Area Scroll Range RGB Brightness Status (Read) Status (Write) 87FC 87FD 87FE 87FF 7 7.1 HSYNC Delay Odd/Even Align reserved Configuration 7 SRC3 VPOL HOP1 FRC3 - SSH3 SPS3 FBPOL BUSY - - - - CC 6 SRC2 HPOL HOP0 FRC2 - SSH2 SPS2 - - H/V HSD6 OEA6 - PLUS 5 SRC1 VOL5 TAS5 FRC1 TAE5 SSH1 SPS1 - FIELD SCON HSD5 OEA5 - ADJ 4 SRC0 VOL4 TAS4 FRC0 TAE4 SSH0 SPS0 - SCRL SCRL HSD4 OEA4 - MIN 3 FLF VOL3 TAS3 FRDN TAE3 SSP3 STS3 BRI3 SCR3 - HSD3 OEA3 - - 2 MSH VOL2 TAS2 FRDE TAE2 SSP2 STS2 BRI2 SCR2 - HSD2 OEA2 - - 1 MOD1 VOL1 TAS1 FRDS TAE1 SSP1 STS1 BRI1 SCR1 - HSD1 OEA1 - - 0 MOD0 VOL0 TAS0 FRDW TAE0 SSP0 STS0 BRI0 SCR0 - HSD0 OEA0 - -
ADDRESS (HEX) 87F0 87F1 87F2 87F3 87F4 87F5 87F6 87F7 87F8
I/O FACILITY I/O ports
handbook, halfpage
The P8xCx70 has 29 I/O lines treated as 29 individual addressable bits or as 4 parallel 8-bit addressable ports, e.g. Ports 0, 1, 2 and 3, with the exception of Port 1 which has only 5 lines available. 7.2 Port type
I/O pin
Q from port latch
n
input data read port pin INPUT BUFFER
MGK547
All I/O port pins are open-drain, bidirectional and require external pull-up resistors. No port options are available for masking.
Fig.3 Open-drain I/O port.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
8 WATCHDOG TIMER (T3)
P8xCx70 family
In addition to the standard timers, an 8-bit Watchdog Timer is also incorporated. When a timer overflow occurs, the microcontroller is reset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the processor running out of control. The timer is incremented every 2 ms. The timer interval between the timer reloading and the occurrence of a reset depends on the reloaded value. This may range from 2 to 512 ms according to the following formula: T timer = ( 256 - T3 value ) x 2 ms 8.1 Watchdog Timer Register (WDT) Watchdog Timer Register (SFR address FFH) 6 D6 Description of the T3 bits SYMBOL D7 to D0 5 D5 4 D4
The Watchdog Timer can only be reloaded if the condition flag WLE in SFR PCON has been previously set HIGH by software. At the moment the counter is loaded WLE is automatically cleared. The Watchdog Timer is controlled by the EW bit in SFR BWC (see Section 11.5). If EW = 1, the Watchdog Timer is enabled and the Power-down mode disabled. If EW = 0, the Watchdog Timer is disabled and the Power-down mode enabled. In the Idle mode the Watchdog Timer and reset circuitry remain active.
Table 4 7 D7 Table 5 BIT
3 D3
2 D2
1 D1
0 D0
DESCRIPTION Watchdog Timer reload value. These 8 bits determine the timer interval. If WDT holds FFH the timer interval is 2 ms. If WDT holds 00H the timer interval is 512 ms.
7 to 0
handbook, full pagewidth
INTERNAL BUS
1/12 fosc
PRESCALER 11-BIT
CLEAR
WDT REGISTER (8-BIT)
LOAD LOADEN
internal reset RESET
RRESET
CLEAR
WLE PCON.4 write T3 INTERNAL BUS
IDL
LOADEN
PCON.0
MGL298
Fig.4 Watchdog Timer block diagram. 1999 Jun 11 11
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
9 REDUCED POWER MODES
P8xCx70 family
In order to reduce power consumption three reduced power modes are available: Standby, Idle and Power-down. 9.1 Standby mode
RETI, the next instruction to be executed will be the one following the instruction that put the device into the Idle mode. Flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during Idle mode. For example, the instruction that writes to the IDL bit can also set or clear one or both flag bits. When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. The second method of terminating the Idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for only two machine cycles to complete the reset operation. Reset redefines all SFRs, but does not affect the on-chip RAM. 9.3 Power-down mode
In Standby mode full CPU functionality is available but all analog functions (including the OSD) are disabled. Power-on reset and the oscillator remain active. The following also remain active during Standby mode. * CPU * External interrupts INT0 and INT1 * T0, T1 and T3 * I2C-bus interface * PWM outputs. The Standby mode is entered by setting the STBY bit in the STBCON register to a logic 1. Recovering from the Standby mode is achieved by setting the STBY bit back to a logic 0. After entering the normal mode a waiting time of 10 s has to be taken into account in order to allow the analog circuitry to stabilize. 9.2 Idle mode
The Power-down operation freezes the oscillator and all on-chip operations stop. The Power-down mode can only be entered if the EW bit in SFR BWC is LOW; then the Power-down mode is entered by setting the PD bit in the PCON register to a logic 1. The instruction which sets the PD bit in PCON is the last instruction executed prior to going into the Power-down mode. The contents of the on-chip RAM and SFRs are preserved. The port pins output the values held by their respective SFRs. In the Power-down mode VDD may be reduced to minimize power consumption. However, the supply voltage must not be reduced until Power-down mode is active, and must be restored before the hardware reset is applied and frees the oscillator. An on-chip delay counter will count 2048 system oscillator cycles before enabling the internal clock. 9.3.1 WAKE-UP FROM POWER-DOWN USING EXTERNAL
INTERRUPTS
Idle mode operation permits all functions to continue to work with the exception that the CPU clock is halted. The following functions remain active during Idle mode: * T0, T1 and T3 (Watchdog Timer) * I2C-bus * External interrupts. 9.2.1 ENTERING IDLE MODE
The instruction that sets the IDL bit in the PCON register is the last instruction executed before entering Idle mode. Once in the Idle mode the system oscillator keeps running but the internal clock is gated away from the CPU, but not gated away from the interrupts, timers and serial port functions. The CPU status is preserved along with the Stack Pointer, Program Counter, Program Status Word and Accumulator. The RAM and all other registers maintain their data during Idle mode. The port pins retain the logical states they were holding at Idle mode activation. 9.2.2 RECOVERING FROM IDLE MODE
If either of the external interrupts INT0 and INT1 is switched to level-sensitive and enabled then the interrupt can be used to wake-up the P8xCx70 from the Power-down mode. To ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 2048 system oscillator cycles. 9.3.2 WAKE-UP FROM POWER-DOWN USING RESET
There are two methods used to terminate the Idle mode. Assertion of any enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating the Idle mode. The interrupt is serviced, and following the instruction 1999 Jun 11 12
The Power-down mode can be terminated by holding the RESET pin HIGH for two machine cycles, this clears the PD bit. The on-chip delay counter will count 2048 system oscillator cycles before enabling the internal clock.
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
9.4 9.4.1 Table 6 7 - Table 7 BIT 7 to 1 0 9.4.2 Control registers STANDBY CONTROL REGISTER (STBCON) Standby Control Register (SFR address 92H) 6 - 5 - 4 - 3 - 2 -
P8xCx70 family
1 -
0 STBY
Description of STBCON bits SYMBOL - STBY These 7-bits are reserved. Standby mode selection. When STBY = 1, the device enters Standby mode. DESCRIPTION
POWER CONTROL REGISTER (PCON)
Idle and Power-down modes are activated by software via the Special Function Register PCON. Table 8 7 - Table 9 BIT 7 to 5 4 3 2 1 0 Power Control Register (SFR address 87H) 6 - Description of PCON bits SYMBOL - WLE GF1 GF0 PD IDL These 3 bits are reserved. Watchdog Load Enable. If WLE = 1, the Watchdog Timer can be loaded. If WLE = 0, the Watchdog Timer cannot be loaded. General purpose flag 1. General purpose flag 0. Power-down mode selection. If PD = 1, the Power-down mode is entered (provided that the EW bit in SFR BWC is LOW). Idle mode selection. If IDL = 1, the Idle mode is entered. If IDL = 0, the Idle mode is inhibited, i.e.normal operation. DESCRIPTION 5 - 4 WLE 3 GF1 2 GF0 1 PD 0 IDL
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
XO
XI interrupts serial ports timer blocks CC
OSCILLATOR CLOCK GENERATOR
CPU
P8xCx70 family
PD IDL
MGL595
Fig.5 Idle and Power-down circuit.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
10 I2C-BUS SERIAL I/O 10.1 The I2C-bus 10.2 Operation modes I2C-bus
P8xCx70 family
This serial port supports the twin line I2C-bus. The I2C-bus consists of a serial data line (SDA) and a serial clock line (SCL). These lines also function as I/O port lines P3.5 and P3.4 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. Full details of the I2C-bus are given in the document "The I2C-bus and how to use it". This document may be ordered using the code 9398 393 40011.
The serial I/O has complete autonomy in byte handling and operates in four modes. * Master transmitter * Master receiver * Slave transmitter * Slave receiver. These functions are controlled by the S1CON register. S1STA is the Status Register whose contents may also be used as a vector to various service routines. S1DAT is the Data Shift Register and S1ADR the Slave Address Register. Slave address recognition is performed by hardware.
handbook, full pagewidth
SLAVE ADDRESS GC S1ADR
SDA
SHIFT REGISTER INTERNAL BUS S1DAT
ARBITRATION LOGIC
SCL
BUS CLOCK GENERATOR
7 S1CON
6
5
4
3
2
1
0
7 S1STA
6
5
4
3
2
1
0
MBC749 - 1
Fig.6 Block diagram of the I2C-bus serial I/O.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
10.3 Serial Control Register (S1CON) Table 10 Serial Control Register (SFR address D8H) 7 CR2 6 ENS1 5 STA 4 STO 3 SI 2 AA
P8xCx70 family
1 CR1
0 CR0
Table 11 Description of S1CON bits BIT 6 SYMBOL ENS1 DESCRIPTION Enable Serial I/O. When ENS1 = 0, the SIO is disabled and reset. The SDA and SCL outputs are in a high-impedance state; P3.4 and P3.5 function as open-drain ports. When ENS1 = 1, the SIO is enabled. The P3.4 and P3.5 port latches must be set to logic 1. START flag. When the STA bit is set in Slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free. If STA is set while the SIO is in Master mode, SIO transmits a repeated START condition. STOP flag. With this bit set while in Master mode a STOP condition is generated. When a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the Slave mode, the STO flag may also be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C-bus interface. However, the SIO hardware behaves as if a STOP condition has been received and releases SDA and SCL. The SIO then switches to the `not addressed' slave receiver mode. The STO flag is automatically cleared by hardware. SIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of the following conditions: * A START condition is generated in Master mode * Own slave address received during AA = 1 * General call address received while S1ADR.0 = 1 and AA = 1 * Data byte received or transmitted in Master mode (even if arbitration is lost) * Data byte received or transmitted as selected slave * STOP or START condition received as selected slave receiver or transmitter. 2 AA Assert Acknowledge. When the AA flag is set, an acknowledge (LOW level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: * Own slave address is received * General call address is received (S1ADR.0 = 1) * Data byte received while device is programmed as a Master receiver * Data byte received while device is a selected Slave receiver. With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested when the `own slave address' or general call address is received. 7 1 0 CR2 CR1 CR0 Clock Rate selection. These three bits determine the serial clock frequency when SIO is in Master mode; see Table 12. The maximum I2C-bus frequency is 400 kHz.
5
STA
4
STO
3
SI
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
Table 12 Selection of SCL frequency in Master mode CR2 0 0 0 0 1 1 1 1 10.4 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fosc DIVISOR 60 1600 40 30 240 3200 160 120
P8xCx70 family
BIT RATE (kHz) at fosc = 12 MHz 200 7.5 300 400 50 3.75 75 100
Status Register (S1STA)
S1STA is an 8-bit read-only Special Function Register. The contents of S1STA may be used as a vector to a service routine. This optimizes response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C-bus interface are given in Table 16. The abbreviations used in Table 16 are defined in Table 15. Table 13 Status Register (SFR address D9H) 7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 0 1 0 0 0
Table 14 Description of S1STA bits BIT 7 to 3 2 to 0 - SYMBOL SC4 to SC0 These 3 bits are held LOW. DESCRIPTION 5-bit status code; see Table 16.
Table 15 Abbreviations used in Table 16 SYMBOL SLA R W ACK ACK DATA MST SLV TRX REC 7-bit slave address read bit write bit acknowledgment (Acknowledge bit = 0) not acknowledge (Acknowledge bit = 1) 8-bit byte to or from the I2C-bus master slave transmitter receiver DESCRIPTION
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
Table 16 Status codes S1STA VALUE MST/TRX mode 08H 10H 18H 20H 28H 30H 38H MST/REC mode 38H 40H 48H 50H 58H SLV/REC mode 60H 68H 70H 78H 80H 88H 90H 98H A0H SLV/TRX mode A8H B0H B8H C0H C8H Miscellaneous 00H own SLA and R have been received. ACK returned own SLA and W have been received; ACK returned arbitration lost while returning ACK SLA and R have been transmitted; ACK received SLA and R have been transmitted; ACK received DATA has been received; ACK returned DATA has been received; ACK returned a START condition has been transmitted a repeated START condition has been transmitted SLA and W have been transmitted; ACK received SLA and W have been transmitted; ACK received DATA of S1DAT has been transmitted; ACK received DATA of S1DAT has been transmitted; ACK received arbitration lost in SLA, R/W or DATA DESCRIPTION
P8xCx70 family
arbitration lost in SLA, R/W as MST; own SLA and W have been received; ACK returned general CALL has been received; ACK returned arbitration lost in SLA, R/W as MST; general CALL has been received previously addressed with own SLA; DATA byte received; ACK returned previously addressed with own SLA; DATA byte received; ACK returned previously addressed with general CALL; DATA byte has been received; ACK returned previously addressed with general CALL; DATA byte has been received; ACK returned a STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX
arbitration lost in SLA, R/W as MST; own SLA and R have been received; ACK returned DATA byte has been transmitted; ACK received DATA byte has been transmitted; ACK received last DATA byte has been transmitted (AA = logic 0) ACK received
bus error during MST mode or SLV mode, due to an erroneous START or STOP condition
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
10.5 Data Shift Register (S1DAT)
P8xCx70 family
This register contains the serial data to be transmitted or data has just been received. Bit 7 is transmitted or received first. Table 17 Data Shift Register (DAH) 7 D7 10.6 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Slave Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as slave receiver/transmitter. The LSB bit (GC) is used to determine whether the general CALL address is recognized. Table 18 Slave Address Register (SFR address DBH) 7 SLA6 6 SLA5 5 SLA4 4 SLA3 3 SLA2 2 SLA1 1 SLA0 0 GC
Table 19 Description of S1ADR bits BIT 7 to 1 0 SYMBOL SLA<6-0> GC own slave address If GC = 0, the general CALL address is not recognized. If GC = 1, the general CALL address is recognized. DESCRIPTION
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
11 INTERRUPT SYSTEM The P8xCx70 has seven interrupt sources, each of which can be assigned one of two priority levels as shown in Fig.7. The four interrupt sources common to the 80C51 are the external interrupts (INT0 and INT1) and the Timer 0 and Timer 1 interrupts. The SIO1 (I2C-bus) interrupt is generated by the S1 flag in the Serial Control Register (S1CON). This flag is set when SFR S1STA is loaded with a valid status code. The CC interrupt is generated by the RCC flag in SFR IRQ1; this flag is set at the end of the selected CVBS slice line. The BUSY interrupt is generated by the RBUSY flag which also resides in SFR IRQ1 and is set by the OSD. 11.1 How interrupts are handled
P8xCx70 family
Note that if an interrupt of higher priority level becomes active prior to S5P2 of the machine cycle labelled C3, then in accordance with the rules it will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed. Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The hardware generated LCALL pushes the contents of the Program Counter on to the stack (but does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt; see Table 20. Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible. Table 20 Interrupt vectors SOURCE INT0 I2C-bus Timer 0 INT1 BUSY Timer 1 CC VECTOR ADDRESS 0003H 002BH 000BH 0013H 0063H 001BH 006BH
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided that LCALL is not blocked by any of the following conditions: 1. An interrupt of equal priority or higher priority level is already in progress. 2. The current machine cycle is not the final cycle in the execution of the instruction in progress (no interrupt request will be serviced until the instruction in progress is completed). 3. The instruction in progress is RETI or any access to the interrupt priority or interrupt enable registers (no interrupt will be serviced after RETI or after a read or write to IP0, IP1, IEN0 or IEN1 until at least one other instruction has been subsequently executed). The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if an interrupt flag is active but not being responded to for one of the above mentioned conditions, if the flag is still inactive when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new.
Additional details on the interrupt operation are given in "Data Handbook IC20, 80C51-Based 8-bit Microcontrollers".
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
INTERRUPT SOURCES PX0
IEN0/1 REGISTERS
IP0/1 REGISTERS
PRIORITY HIGH LOW
S1 INTERRUPT POLLING SEQUENCE GLOBAL ENABLE
MGR378
T0
PX1
BUSY
T1
CC
Fig.7 The interrupt structure.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
11.2 Interrupt enable structure
P8xCx70 family
Each interrupt source can be individually enabled or disabled by setting or clearing its associated bit in the Interrupt Enable Registers (IEN0 and IEN1). All interrupt sources can also be globally disabled by clearing the EA bit in SFR IEN0. The Interrupt Enable Registers are described in Sections 11.2.1 and 11.2.2. 11.2.1 INTERRUPT ENABLE REGISTER 0 (IEN0)
Table 21 Interrupt Enable Register 0 (SFR address A8H) 7 EA 6 - 5 ES1 4 - 3 ET1 2 EX1 1 ET0 0 EX0
Table 22 Description of the IEN0 bits BIT 7 6 5 4 3 2 1 0 11.2.2 SYMBOL EA - ES1 - ET1 EX1 ET0 EX0 DESCRIPTION General enable/disable control. When EA = 0, no interrupt is enabled. When EA = 1, any individually enabled interrupt will be accepted. This bit is not used; program to a logic 0 for future compatibility reasons. Enable I2C-bus SIO interrupt. This bit is not used; program to a logic 0 for future compatibility reasons. Enable Timer 1 interrupt. Enable external interrupt 1. Enable Timer 0 interrupt. Enable external interrupt 0.
INTERRUPT ENABLE REGISTER 1 (IEN1)
Table 23 Interrupt Enable Register 1 (SFR address E8H) 7 - 6 ECC 5 EBUSY 4 - 3 - 2 - 1 - 0 -
Table 24 Description of the IEN1 bits BIT 7 6 5 4 to 0 SYMBOL - ECC EBUSY - DESCRIPTION This bit is not used; program to a logic 0 for future compatibility reasons. Enable external interrupt 8 (CC data ready). Enable external interrupt 7 (BUSY interrupt). These 5 bits are not used; program to logic 0s for future compatibility reasons.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
11.3 Interrupt priority structure Table 25 Interrupt priority SOURCE INT0 I2C-bus Timer 0 INT1 BUSY Timer 1 CC Note
P8xCx70 family
Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the Interrupt Priority Registers (IP0 and IP1). These registers are described in Sections 11.3.1 and 11.3.2. A low priority interrupt may be interrupted by a high priority interrupt level interrupt. A high priority interrupt routine cannot be interrupted by any other interrupt source. If two interrupts of different priority occur simultaneously, the high priority level request is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence. This second priority structure is shown in Table 25.
PRIORITY WITHIN LEVEL(1) highest lowest
1. The `priority within level' structure is only used to resolve simultaneous requests of the same priority level.
11.3.1
INTERRUPT PRIORITY REGISTER 0 (IP0)
Table 26 Interrupt Priority Register 0 (SFR address B8H) 7 - 6 - 5 PS1 4 - 3 PT1 2 PX1 1 PT0 0 PX0
Table 27 Description of IP0 bits BIT(1) 7 to 6 5 4 3 2 1 0 Note 1. Where: logic 0 = low priority; logic 1 = high priority. SYMBOL - PS1 - PT1 PX1 PT0 PX0 I2C-bus SIO interrupt priority level. This bit is not used, program to a logic 0 for future compatibility reasons. Timer 1 interrupt priority level. External interrupt 1 priority level. Timer 0 interrupt priority level. External interrupt 0 priority level. DESCRIPTION This bit is not used, program to a logic 0 for future compatibility reasons.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
11.3.2 INTERRUPT PRIORITY REGISTER 1 (IP1)
P8xCx70 family
Table 28 Interrupt Priority Register 1 (SFR address F8H) 7 - 6 PCC 5 PBUSY 4 - 3 - 2 - 1 - 0 -
Table 29 Description of the IP1 bits BIT 7 6 5 4 to 0 11.4 SYMBOL - PCC PBUSY - DESCRIPTION This bit is not used, program to a logic 0 for future compatibility reasons. CC interrupt priority level, fixed to a logic 1. BUSY interrupt 7 priority level, fixed to a logic 1. These 5 bits are not used, program to logic 0s for future compatibility reasons.
Interrupt Request Register 1 (IRQ1)
An interrupt request from the Closed Caption Data Slicer or from the OSD will be flagged by setting the related bit in the Interrupt Request Register 1 to a logic 1. These bits must be reset to logic 0s by software. Table 30 Interrupt Request Register 1 (SFR address 98H) 7 - 6 RCC 5 RBUSY 4 - 3 - 2 - 1 - 0 -
Table 31 Description of IRQ1 bits BIT 7 6 5 4 to 0 SYMBOL - RCC RBUSY - DESCRIPTION This bit is not used, program to a logic 0 for future compatibility reasons. Request for CC interrupt, active HIGH. Request for BUSY interrupt, active HIGH. These 5 bits are not used, program to logic 0s for future compatibility reasons.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
11.5 11.5.1 Busy interrupt and Watchdog Timer control BUSY INTERRUPT AND WATCHDOG CONTROL REGISTER (BWC)
P8xCx70 family
The BUSY signal can generate an interrupt (PX7) to the CPU if enabled by IEN1.5, the vector address is 0063H. This register is used to enable/disable the BUSY interrupt and the Watchdog Timer. Table 32 BUSY interrupt and Watchdog Control Register (SFR address EBH) 7 - 6 - 5 - 4 - 3 - 2 - 1 EW 0 BUSY
Table 33 Description of the BWC bits BIT 7 to 2 1 0 SYMBOL - EW BUSY These 6 bits are not used. Enable Watchdog Timer. If EW = 0, then the Watchdog Timer is disabled. If EW = 1, then the Watchdog Timer is enabled and the Power-down mode is disabled. When BUSY = 0, an active external interrupt will generate an interrupt to the CPU. When BUSY = 1, external interrupts are disabled. It is not recommended to update the display RAM when the BUSY signal is active (LOW), due to the effect it may have on the OSD display. The display RAM can be updated when the BUSY signal is inactive. 11.5.2 INTERRUPT REQUEST (RBUSY) DESCRIPTION
RBUSY is bit 5 of the SFR IRQ1 (address 98H). A falling edge of the active BUSY signal generates a pending interrupt to the CPU and forces the RBUSY bit HIGH. In the service routine, this bit should be cleared before returning to the main routine. As long as RBUSY is HIGH, a pending interrupt is always present. Each time BUSY is activated by a falling edge, the RBUSY is set HIGH. If the interrupt is not served by the next falling BUSY edge, then RBUSY is written to HIGH again and no error of overrun is indicated.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
12 OSCILLATOR CIRCUITRY The on-chip oscillator circuitry of the P8xCx70 is a single-stage inverting amplifier biased by an internal feedback resistor. For operation as a standard quartz oscillator or when using an external ceramic resonator, external components are needed and should be connected as shown in Fig.8. In the Power-down mode the oscillator is stopped and both XI and XO are pulled HIGH. The inverting amplifier and feedback resistor are both switched off to ensure no current will flow regardless of the voltages at XI and XO. To drive the device with an external clock source, apply the external clock signal to XI, and leave XO to float. There is no requirement on the duty cycle of the external clock, because the external clock is divided-by-two using a flip-flop before feeding the internal clocking circuitry. The operating frequency of crystal oscillator is fixed at 12 MHz.
P8xCx70 family
The reset mechanism is illustrated in Fig.9. Each reset source will cause the internal reset signal POC to become active. The CPU responds by executing an internal reset putting the internal registers into a defined state as detailed in Table 34. 13.1 External reset
The reset pin RESET is connected to a Schmitt trigger for noise reduction (see Fig.9). A reset is accomplished by holding the RESET pin HIGH for at least 2 machine cycles (24 system clocks), while the oscillator is running. If the RESET pin is connected to VDD via a capacitor as shown in Fig.9, an automatic reset can be obtained by switching on VDD, The VDD rise time must not exceed 10 ms and the capacitor should be at least 10 F. The decrease of the RESET pin voltage depends on the capacitor and the internal resistor RRESET. The voltage must remain above the lower threshold level for a minimum period determined by the oscillator start-up time plus 2 machine cycles. For the P8xCx70 an external capacitor value of 10 F is needed. 13.2 Power-on reset
handbook, halfpage
An on-chip Power-on reset circuit detects supply voltage variations and generates a Power-on reset pulse accordingly; see Fig.10.
XI XO
MBE311
In the case of supply voltage ramp-up, the power-on reset signal follows the ramp-up of the supply voltage. When the trip level (Vt) is reached, the power-on reset signal will be maintained for a time period (Tp) before reverting back to its LOW state. In the case of supply voltage drop, after the trip level (Vt) is reached, the power-on reset signal will respond within Tr. The internal reset will remain active until Tp after the Vt has been exceeded. The time interval (Tp) is used to guarantee a complete power-on reset pulse so that this signal can trigger the internal reset signal. However, to ensure the oscillator is stable before the controller starts, the clock is gated away from the CPU for a further 2048 oscillator cycles. 13.3 Watchdog Timer overflow
For quartz crystal or ceramic resonator.
Fig.8 Oscillator configuration.
13 RESET There are three ways to invoke a reset and initialize the P8xCx70: * Via the external RESET pin * Via the on-chip Power-on reset circuitry * Via a Watchdog Timer overflow.
The length of the output pulse from T3 is 3 machine cycles. A pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
VDD 10 F SCHMITT TRIGGER
RSTOUT RESET 8 k RRESET
RESET CIRCUITRY
overflow Watchdog Timer on-chip circuit Power-on-reset
POC
MBK878
Fig.9 On-chip reset configuration.
handbook, full pagewidth
Vt Vt
Supply voltage
Power-onreset
Oscillator
CPU running 2048 clocks Tp START-UP Tp 2048 clocks
MGR379
Fig.10 Power-on reset switching level.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
Table 34 The reset value of the SFRs SFR ADDR 80H 81H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 92H 96H 98H A0H A6H A8H B0H B6H B7H B8H C6H D0H D6H D7H P0 SP PWM0 PCON TCON TMOD TL0 TL1 TH0 TH1 P1 STBCON PWM1 IRQ1 P2 PWM2 IEN0 P3 PWM3 SL IP0 PWM4 PSW PWM5 CCData1 REGISTER CONTENT(1) 1111 1111 0000 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXX1 1111 XXXX XXX0 0000 0000 X00X XXXX 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 XXX1 0101 XX0X 0000 0000 0000 0000 0000 0000 0000 0000 0000 Note SFR ADDR D8H D9H DAH DBH E0H E6H E7H E8H EAH EBH F0H F4H F5H F6H F8H FFH 87F0H 87F1H 87F2H 87F3H 87F4H 87F5H 87F6H
P8xCx70 family
REGISTER S1CON SISTA S1DAT S1ADR ACC PWM6 CCData2 IEN1 AFCON BWC B P1SEL PWM8 PWM7 IP1 T3 DCR TVPR THPR FCR TAER SSACR SRRR
CONTENT(1) X000 0000 1111 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 X000 000X XXXX XX1X 0000 0000 XXX0 X000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
1. X = undefined. The internal RAM is not affected by reset.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
14 PIN FUNCTION SELECTION Ports 0, 1 and 3 are dual purpose ports and can be configured as port lines or selected as alternative functions. Selection of the pin as a port line or alternative function is achieved using the appropriate SFR as described in Sections 14.1, 14.2.1 and 14.3. 14.1 Port 0 pin function selection
P8xCx70 family
When using these pins as general I/O port lines (PWMnE = 0), writing is done to the P0 latch and reading at either the P0 latch or the port pins. No special control is required for this selection. 14.2 Port 1, P3.4 and P3.5 pin function selection
Port 0 is an 8-bit port which can be configured as eight bidirectional port lines (P0.0 to P0.7) or as eight 7-bit PWM outputs (PWM1 to PWM8). Each 7-bit PWM output can be selected by setting the PWMnE bit in its associated PWMn register to a logic 1 (see Section 15.1). When using these pins as PWM outputs, the system software needs to keep track of its I/O status and avoid reading from these ports. 14.2.1 PORT 1 SELECTION REGISTER (P1SEL)
Port 1 is a 4-bit port which can be configured as four bidirectional port lines (P1.0 to P1.3) or as three AFT inputs (AFT0 to AFT2) and one 7-bit PWM output (PWM0). The AFT inputs are selected using the Port 1 Selection Register (P1SEL) as described in Section 14.2.1. This register also selects the I2C-bus functions of P3.4 and P3.5. The PWM function of the P1.3/PWM0 pin is enabled by setting the PWM0E bit in SFR PWM0 to a logic 1.
Table 35 Port 1 Selection Register (SFR address F4H) 7 - 6 - 5 - 4 I2CE 3 - 2 AFT2E 1 AFT1E 0 AFT0E
Table 36 Description of P1SEL bits BIT 7 6 5 4 SYMBOL - - - I2CE When I2CE = 1, pins 49 and 50 are enabled as alternative functions SCL and SDA respectively. When I2CE = 0, pins 49 and 50 are enabled as general I/O port lines P3.4 and P3.5 respectively. This bit is not used. When AFT2E = 1, pin 11 is selected as AFT2 input. When AFT2E = 0, pin 11 is selected as general I/O port line P1.2. When AFT1E = 1, pin 10 is selected as AFT1 input. When AFT1E = 0, pin 10 is selected as general I/O port line P1.1. When AFT0E = 1, pin 9 is selected as AFT0 input. When AFT0E = 0, pin 9 is selected as general I/O port line P1.0. These 3 bits are reserved. DESCRIPTION
3 2 1 0
- AFT2E AFT1E AFT0E
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
14.3 Port 3 pin function selection
P8xCx70 family
Port 3 is an 8-bit port which can be configured as eight bidirectional port lines (P3.0 to P3.7) or as two external interrupts (INT0 and INT1), two timer/counter inputs (T0 and T1) and the two I2C-bus lines (SDA and SCL). Port lines P3.6 and P3.7 have no alternative functions. To configure these pins as alternative functions, the corresponding bit in the Port 3 latch (P3) should be programmed to a logic 1 and the corresponding bit in SFR IEN0 also set to a logic 1. 14.3.1 PORT 3 LATCH (P3)
Table 37 Port 3 Latch (SFR address B0H) 7 P37 6 P36 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30
Table 38 Description of P3 bits BIT 7 6 5 4 3 2 1 0 SYMBOL P37 P36 P35 P34 P33 P32 P31 P30 When P35 = 1, pin 50 is used as SDA if the I2CE bit in SFR P1SEL is a logic 1. Otherwise pin 50 is general I/O port line P3.5. When P34 = 1, pin 49 is used as SDL if the I2CE bit in SFR P1SEL is a logic 1. Otherwise pin 49 is general I/O port line P3.4. When P33 = 1, pin 48 is used as Timer 1 input if the ET1 bit in SFR IEN0 is a logic 1. Otherwise pin 48 is general I/O port line P3.3. When P32 = 1, pin 47 is used as external interrupt INT0 if the EX0 bit in SFR IEN0 is a logic 1. Otherwise pin 47 is general I/O port line P3.2. When P31 = 1, pin 46 is used as Timer 0 input if the ET0 bit in SFR IEN0 is a logic 1. Otherwise pin 46 is general I/O port line P3.1. When P30 = 1, pin 45 is used as external interrupt INT1 if the EX1 bit in SFR IEN0 is a logic 1. Otherwise pin 45 is general I/O port line P3.0. No alternative function available. DESCRIPTION
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
15 7-BIT PWM DAC
P8xCx70 family
The P8xCx70 has nine PWM DAC outputs (PWM0 to PWM8) for analog control e.g. volume, balance, bass, treble, brightness, contrast, sharpness, hue and saturation. Each PWM output generates a pulse pattern with a repetition rate of 1128fPWM. The analog value is determined by the ratio of the HIGH-time and the repetition time. A DC voltage proportional to the PWM control setting is obtained by means of an external integration network (low-pass filter). The polarity of each PWM output is fixed to active HIGH. The HIGH-time of a PWMn output (within one PWM cycle time) may be calculated as shown in Equation (1). t HIGH = PWMn x t 0 Where PWMn is the contents of PWMn data latch; t0 = 1/fPWM and fPWM = 14fxtal. 15.1 SFRs for PWM output control (1)
The alternative PWM functions of Port 0 pins are enabled by writing a logic 1 to the PWMnE bit of the associated Special Function Register. When setting the PWMnE bit to a logic 0, the associated pin becomes a general I/O port line. Table 39 SFR data registers for the 7-bit PWMs REGISTER PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 ADDRESS 86H 96H A6H B6H C6H D6H E6H F6H F5H 7 PWM0E PWM1E PWM2E PWM3E PWM4E PWM5E PWM6E PWM7E PWM8E 6 data6 data6 data6 data6 data6 data6 data6 data6 data6 5 data5 data5 data5 data5 data5 data5 data5 data5 data5 4 data4 data4 data4 data4 data4 data4 data4 data4 data4 3 data3 data3 data3 data3 data3 data3 data3 data3 data3 2 data2 data2 data2 data2 data2 data2 data2 data2 data2 1 data1 data1 data1 data1 data1 data1 data1 data1 data1 0 data0 data0 data0 data0 data0 data0 data0 data0 data0
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
16 AFT INPUTS (ADC)
P8xCx70 family
The P8xCx70 has 3 ADC channels each with 4-bit resolution. One channel is intended to measure the level of the key pad signals. This is achieved by comparing the AFT signal with the output of a 4-bit DAC. The compare time of the AFT is not greater than 8 s at 12 MHz. Adding NOP instructions is recommended in between the instructions which change the reference voltage or channel and the instructions which read the AFTC register bit. Ensure that pins 9, 10 and 11 are configured as AFT functions before use (see Chapter 14). The conversion time (TAFC) of an AFT (4-bit output) is calculated as shown below. T AFC = ( T CPU + 8 ) x 4 s where: T CPU = ( number of instructions to program 4-bit DAC ) x ( instruction cycle time )
handbook, full pagewidth
DERIVATIVE PORT SELECTOR EN2 P1.0/AFT0 P1.1/AFT1 P1.2/AFT2 Vref COMPARATOR EN AFT CHANNEL SELECTOR 3 AFT2E AFT1E AFT0E EN1 EN0
Internal bus
AFT function enable (SFR address F4H) AFTC (SFR address EAH)
Channel selection (SFR address EAH)
AFTH1
AFTH0 4-BIT DAC
AFTL3
AFTL2
AFTL1
AFTL0
(SFR address EAH)
Internal bus
MGL596
Fig.11 AFT block diagram.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
16.1 AFT Control Register (AFCON)
P8xCx70 family
Table 40 AFT Control Register (SFR address EAH) 7 - 6 AFTH1 5 AFTH0 4 AFTL3 3 AFTL2 2 AFTL1 1 AFTL0 0 AFTC
Table 41 Description of AFCON bits BIT 7 6 5 4 3 2 1 0 SYMBOL - AFTH1 AFTH0 AFTL3 AFTL2 AFTL1 AFTL0 AFTC Reserved. AFT channel selection. These two bits are used to select the AFT channel; see Table 42. AFT reference voltage level selection. These four bits are used to select the analog output voltage (Vref) of the 4-bit DAC. Vref is calculated as shown in the equation below: V DD V ref = --------- x ( DAC value + 1 ) 16 AFT compare result. If AFTC = 0; the AFT input voltage is lower than the reference voltage. If AFTC = 1; the AFC input voltage is higher than the reference voltage. DESCRIPTION
Table 42 Selection of AFT channel AFTH1 0 0 1 1 AFTH0 0 1 0 1 AFT0 AFT1 AFT2 illegal code CHANNEL SELECTED
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
17 DATA SLICER AND CC COMMAND INTERPRETER The P8xCx70 family contains a Data Slicer which slices Closed Caption data from the CVBS signal. The slice line is programmable between lines 17 to 23. CC command interpretation has to be done by a Command Interpreter which is a relocatable software module. It interprets the 2 bytes that have been sliced off the selected CVBS line and prepares the display RAM in the OSD block for proper Closed Caption and OSD display function. The composite data signal contained within the active portion of the CVBS line consists of a 7 cycle sine-wave clock run-in burst, 3 start bits and 16 bits of data. These 16 bits consist of two 8-bit alphanumeric characters formulated according to the American Standard Code for Information Interchange (ASCII; x3.4-1967) with odd parity. The clock rate is 0.5035 MHz which is 32fh (horizontal frequency). The clock run-in burst data packet is 50 IRE units (peak-to-peak). Data is sent with the LSB (bit D0) being sent first and the MSB (bit D7, the parity bit) sent last. Figure 13 illustrates CVBS timing. 17.1 Data Slicer
P8xCx70 family
It also provides a line rate ramp, from which the line based timing signals for the data detection section may be decoded. 17.1.3 DATA DETECTOR
The data detector consists of a low-pass filter which screens out signals above 1 MHz (mainly noise); a DC-loop, which removes DC offset and low frequency interference and adjusts the slice level continuously; an amplitude estimator, which provides the DC-loop with an estimation of signal strength to enable an accurate adaptive slicing level to be calculated and also aids in the detection of signal loss or absence of Closed Caption data and a clock synchronizer, which provides accurate centre-on-the-incoming data bits clock to the byte extractor. 17.1.4 BYTE EXTRACTOR
The Composite Video Baseband Signal input should be a signal which is nominally 1 V(p-p) with sync tips negative and band limited to 3% of the standard frequency. The Data Slicer consists of: * 7-bit ADC which converts the analog CVBS signal into digital data for extraction * Sync separator and bit clock recovery * Data Detector, which extracts the serial stream of bits from the video signal * Byte Extractor, which performs serial-to-parallel conversion. 17.1.1 ANALOG-TO-DIGITAL CONVERTER
The Byte extractor extracts data bytes from the sliced bit stream using the clock provided by the data detector block, performs serial-to-parallel conversion, then feeds the 2 data bytes to a pair of registers (CCData1 and CCData2) which hold the 2 data bytes for CC command interpretation. At the end of the selected CVBS line the byte extractor will issue the CC interrupt to the CPU. This interrupt will be generated regardless of whether new data has been received or not. 17.2 Command Interpreter
A 7-bit ADC generates a clean CMOS level data signal by slicing the analog CVBS signal using a 6 MHz clock. The ADC error is 12 LSB across the full range (2 V(p-p)). 17.1.2 SYNC SEPARATION AND ACQUISITION TIMING
The Command Interpreter is implemented in software. It is used for data field selection, code interpretation and addressing of the display RAM. It reads the CCData1 and CCData2 registers, checks for the correct parity, field and channel number. When the data received is the correct data, the bytes are passed on to the logic decoder software that interprets the data and addresses the display RAM. The CC770 Closed Caption software supports the three main modes CAPTION, TEXT and XDS. These operation modes can be selected by the user. For the first two modes, the data reception will be done in one of two operating channels C1 or C2 separately for Field 1 or Field 2 of the video frame. The XDS mode is only available in Field 2.
This block contains an acquisition phase-locked loop which locks onto the incoming video line syncs, with a frequency error of 3% for a varying frequency error and a wide locking range, such as a VCR.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
CVBS
LEVEL SHIFT AND ADC
DATA DETECTOR
BYTE EXTRACTOR
CC interrupt CCData1, CCData2
SYNC SEPARATOR
BIT CLOCK RECOVERY
MGR278
Fig.12 Data Slicer block diagram.
handbook, full pagewidth
Start bit clock pulse in burst
50 25 20 0 -20 -40 Hsync IRE units clock run-in (7 cycles) Program colour burst Byte 1 Byte 2
MGK588
D0
D6 P D0
D6 P
Odd/Even field
Fig.13 Line 21 CVBS Transmission Format.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
17.3 17.3.1 Closed Caption registers SLICE LINE REGISTER (SL)
P8xCx70 family
The Data Slicer contains a software programmable Slice Line Register to extract data from one scan-line out of a range of scan-lines 17 to 23. Table 43 Slice Line Register (SFR address B7H) 7 - 6 - 5 - 4 CS4 3 CS3 2 CS2 1 CS1 0 CS0
Table 44 Description of SL bits BIT 7 to 5 4 to 0 SYMBOL - CS4 to CS0 These 3 bits are not used. Scan-line select. These 5 bits are used to select one scan line from scan-lines 17 to 23. For example, the value `10001' selects scan-line 17; the value `10111' selects scan-line 23. DESCRIPTION
17.3.2
CLOSED CAPTION DATA REGISTER 1(CCDATA1)
There are two Closed Caption Data Registers: CCData1 and CCData2. At the beginning of the selected CVBS line these registers will be reset to 00H. The received data will be written into the register at the end of the selected CVBS line, then also the CC interrupt will be issued. If no data was received, the content of the registers will stay at 00H. Table 45 Closed Caption Data Register 1 (SFR address D7H) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Table 46 Description of the CCData1 bits BIT 7 to 0 17.3.3 SYMBOL D7 to D0 DESCRIPTION Byte 1 as sliced from the selected CVBS line.
CLOSED CAPTION DATA REGISTER 2 (CCDATA2)
Table 47 Closed Caption Data Register 2 (SFR address E7H) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Table 48 Description of CCData2 bits BIT 7 to 0 SYMBOL D7 to D0 DESCRIPTION Byte 2 as sliced from the selected CVBS line.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18 CC/OSD DISPLAY FUNCTION P8xCx70 contains a display function which covers both OSD and Closed Caption display requirements. The design is targeted for the US market. The RGB outputs are analog signals derived from a DAC together with the FB (fast blanking) control signal. 18.1 Key features
P8xCx70 family
* Character and attribute coding, `set at' and `set after' - All serial Mode 0 are `set at', i.e., valid from the character set - Serial Mode 1 at first character position of each row are `set at' - Serial Mode 1 after first character position are `set after', i.e. valid from the next character onward. * Colour Look-up Table (CLUT) - Soft colours: 16 entries CLUT; each entry selected out of 4096 possible colours (4 bits each for R, G and B) - Primary background screen colour: 16, selected from CLUT - Foreground colours: 8 + 8, on a parallel (character-by-character) basis selected from CLUT - Background colours: 16, on a serial (row-by-row) basis selected from CLUT. * Display character size - Horizontal display size: 1x or 2x OSD clock periods per dot, on a serial basis - Vertical display size: 1x or 2x scan-lines per dot, on a serial basis. * Special attributes - Flash, Italic, Underline, Overline attributes via attribute coding on a serial basis, Mode 0 `set at' - Proportional spacing supported - Fringing (shadowing): independent north, south, east and/or west fringing on a screen (applied to all characters displayed) basis via a control register - Boxing attribute via attribute coding on a serial basis, both Mode 0 and Mode 1 possible - Meshing attribute on a screen basis via control register; background colour areas are modified to display background colours and video alternately, provided in Mixed Video display mode - Flashing (blinking) on a serial basis, Mode 0 `set at'; flashing frequency: 50% duty, 1 or 2 Hz, done via a control register.
* Fonts - 176 character fonts in masked ROM, each font made up of a 12 x 16 ROM matrix - Each character displayed as 12 x 13 matrix - Special graphic character fonts: maximum 16 characters; each uses masked ROM contents of 2 normal characters; up to 4 different colours can appear in a character - Character OTP EPROM: 33792 bits (176 x 12 x 16). * Display RAM - Display RAM: 560 words of 12 bits/word - Maximum displayed characters: 544. * Screen layout, primary background area: - Vertical range: line 6 of Field 1 (line 269 of Field 2) to leading edge of VSYNC - Horizontal range: 8 s after trailing edge of HSYNC, 56 s duration - Defines an area with screen colour, large enough that no adjustment is needed. * Screen layout, CC/OSD text area: - Vertical offset: 0 to 63 scan-lines from trailing edge of VSYNC - Horizontal offset: 0 to 63 characters from trailing edge of HSYNC plus 0 to 3 quarters character fine offset - Maximum CC/OSD rows: 16 (208 scan-lines) - Maximum CC/OSD columns: 48 (12 MHz OSD clock). * Character and attribute coding, display control modes - Attribute coding is done by combining with character coding in display RAM - Parallel mode: control display feature on a character by character basis, i.e. to a character only - Serial mode: apply to a group of characters, valid to all characters displayed on the same display frame after set till modified.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
* Automatic soft scroll - Programmable soft scroll display area height up to 16 rows - Programmable soft scroll display area top row - Programmable row range for soft scroll - Scroll map maintained in display RAM; number of entries equals scroll display area height, up to 16 entries; display RAM positions occupied not usable for coding display characters. * Miscellaneous - Programmable HSYNC and VSYNC active polarity - Programmable FBL (fast blanking) and R, G and B (during line fly-back periods) polarity - 16 level RGB brightness control - Video, Full Text, Mixed Screen Colour, Mixed Video display modes. 18.2 18.2.1 Display features FLASH 18.2.4 ITALICS
P8xCx70 family
The size of the fringe is independent of the size attributes and always remains 1 scan-line vertically and 1 pixel horizontally for even and odd field. Fringing is only effective within the text area and will not extend over the text area borders. Fringing will cross the borders of boxes in the horizontal direction, but will not cross between rows in the vertical direction. Special facilities are provided for combined characters (see Section 18.10). 18.2.3 SIZE
Two sizes are offered in both horizontal and vertical directions. The sizes available are normal, double height/width and any combinations of these. The attribute settings are always valid for a whole row. Mixing of sizes within a row is not possible. The first character in the row must be the serial attribute, Mode 1 if the default of normal size is to be overridden. These attributes will be ignored in any other position. For additional details see Section 18.3.2.
This attribute is valid from the time set until end of row or otherwise modified. Flashing causes the foreground colour pixels to be displayed as background pixels. This means that the fringing, if set, will only be visible when the foreground colour pixels are displayed as foreground colour. The flash frequency can be set to either 1 or 2 Hz (see Section 18.4.5). 18.2.2 FRINGING
This attribute is valid from the time set until end of row or otherwise modified. This attribute causes the character foreground pixels to be offset horizontally by 1 pixel per 4 scan-lines (interlaced mode); see Fig.14. The base is the bottom left character matrix pixel. The pattern of the character will be indented 1 pixel every 2 scan-lines per field, starting from the base of the character. Fringing is shifted accordingly. 18.2.5 PROPORTIONAL SPACING
This attribute is valid from the time set until end of row or otherwise modified. Fringing causes an edge (fringe) to be put around the foreground pixels. Fringing is an attribute that can be applied to characters providing a shadow around the shape of the foreground information. The fringe is 1 line wide in the vertical direction and 1 pixel wide in the horizontal direction. Fringing applies to all characters except those in columns 8 and 9.
The character font ROM in column A, contains the half-width characters: f, i, j, l and t. These characters have a width of only 6 pixels instead of the normal 12. Examples of half-width characters are shown in Fig.15. If some of the characters are not used for depicting narrow characters they may be used as normal. In this case they are accessible via column D (see Fig.27).
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
0 0 1 2 3 4 5 6 7 8 field 1 field 2 9 10 11 12
2
4
6
8
10
0
2
4
6
8
10 indented by 6
indented by 5
indented by 4
indented by 3
indented by 2
indented by 1
not indented
MGL146
Fig.14 Italics.
handbook, full pagewidth
MGL147
Fig.15 Proportional spacing.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.2.6 COLOUR LOOK-UP TABLE (CLUT)
P8xCx70 family
A Colour Look-up Table with 16 colours is provided. The colours are programmable from a palette of 4096 (4 bits per R, G and B). The CLUT is defined by writing data to the RAM as described in Section 18.6. Table 49 CLUT colour values RED<3-0> 11 0 1 18.2.7 10 0 1 9 0 1 8 0 1 7 0 1 GREEN<3-0> 6 0 1 5 0 1 4 0 1 3 0 1 BLUE<3-0> COLOUR VALUE 2 0 1 1 0 1 0 0 1 lowest value highest value
FAST BLANKING POLARITY
The polarity of the Fast Blanking signal (FBL) can be inverted. When inverted the values of the RGB outputs during line fly-back periods are also inverted. The polarity is set using the FBPOL bit in the RGB Brightness Register (see Section 18.9.8). Table 50 RGB blanking interval values RED<3-0> FBOL 11 0 1 0 1 10 0 1 9 0 1 8 0 1 7 0 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 Normal operation Inverted Fast Blanking signal GREEN<3-0> BLUE<3-0> CONDITIONS
Table 51 Fast Blanking signal polarity FBPOL 0 0 1 1 18.2.8 RGB BRIGHTNESS CONTROL FBL 1 0 0 1 CONDITION RGB display Video display RGB display Video display
A brightness control is provided that allows the RGB output voltages to be modified. The brightness is set using the BRI0 to BRI3 bits in the RGB Brightness Register (see Section 18.9.8). Table 52 RGB brightness selection BRI3 0 1 BRI2 0 1 BRI1 0 1 BRI0 0 1 RGB BRIGHTNESS lowest value highest value
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.2.9 FOREGROUND COLOUR
P8xCx70 family
18.2.13 BACKGROUND DURATION The background duration attribute can be set with the Serial Mode 1 attribute, see Section 18.3.2. In combination with the End Of Row attribute (see Section 18.2.17), it forces the background colour to be displayed on the row until the end of the text area is reached. When set, this attribute takes effect from the current position until the end of the text display as defined in the Text Area End Register (see Section 18.9.5). 18.2.14 UNDERLINE This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then it is set from the next character onwards (see Section 18.3.2). The underline attribute causes the characters to have the bottom scan-line of the character cell forced to foreground colour, including spaces. If background duration is set, then underline is set until the end of the text area. 18.2.15 OVERLINE This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then it is set from the next character onwards (see Section 18.3.2). The overline attribute causes the characters to have the top scan-line of the character cell forced to foreground colour, including spaces. If background duration is set, then overline is set until the end of the text area. 18.2.16 SPECIAL GRAPHIC CHARACTERS Several special characters are provided for special effects. These characters provide a choice of 4 colours within a character cell. The number of characters is limited to 16. Characters are stored in columns 8 and 9 of the ROM table (32 ROM characters). Each character uses the ROM contents of 2 normal characters. Addressing is therefore done using only the even character addresses. The pixel planes are stored in adjacent character locations, always starting with an even character. The pixel plane 0 is stored in the even character and pixel plane 1 is stored in the odd character ROM position There is no fringing possible for these characters.
The foreground colour can be chosen from 8 colours on a character-by-character basis. Two sets of 8 colours are provided. A serial attribute switches between the banks (see Serial Mode 1, bit 7). The colours are the CLUT entries 0 to 7 or 8 to 15. 18.2.10 BACKGROUND COLOUR This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then the colour is set from the next character onwards (see Section 18.3.2). The background colour can be chosen from all 16 CLUT entries. 18.2.11 BOXES This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then it is set from the next character onwards (see Section 18.3.2). In text mode the background colour is displayed regardless of the setting of the box attribute bit. Boxes take affect only during mixed mode, where boxes are set in this mode the background colour is displayed. Character locations where boxes are not set show video/screen colour (depending on the setting in the Display Control Register) instead of the background colour. 18.2.12 MESHING Meshing effects the background colour: * In text mode all background colour will be meshed * During mixed modes the background colour will only be displayed where boxes are active, therefore meshing will only be displayed inside these areas. The appearance of the background colour is modified by the meshing control bit (MSH). If meshing is set then the background pixels, where displayed, are alternately displayed at pixel rate in the background colour and as video/screen colour, depending on which of the mixed modes is set. The structure is offset by 1 pixel from scan-line to scan-line, thus achieving a checker board display of the background colour. Meshing is set in the Display Control Register, see Section 18.9.1.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
If some of the characters are not used for depicting special characters they may be used as normal. In this case they are accessible via the columns B and C (see Section 18.10). The four colours are allocated as shown in Table 53. An example of a special character is shown in Fig.16. If the screen colour is transparent (implicit in Mixed mode) and inside the object the box attribute is set, then the object is surrounded by video. If the box attribute is not set the background colour inside the object will also be displayed as transparent. Table 53 Special character colours PLANE1 0 0 1 1 PLANE0 0 1 0 1 COLOUR ALLOCATION background colour foreground colour foreground colour 6 or 14 depending on the set bank foreground colour 7 or 15 depending on the set bank 18.2.17 END OF ROW
P8xCx70 family
The number of characters in a row is flexible and can be determined by the end of row bit in the Serial Mode 1 character attribute, however the maximum number of characters is determined by the setting of the text area start and the text area end register. The total number of characters displayed on a page is limited by the internal RAM size. The characters are stored sequential in the memory.
handbook, full pagewidth
background colour "set at" (Mode 0)
serial attribute
background colour "set after" (Mode 1)
VOLUME
background colour foreground colour 7 foreground colour normal character foreground colour 6
special character
MGK550
Fig.16 Special character example.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.3 Character and attribute coding * 1x size * Flash off * Overline off * Underline off * Italics off * Display mode = superimpose * Fringing off
P8xCx70 family
Character coding is split into character oriented attributes (parallel) and character group coding (serial). The serial attributes take effect at the set position and remain effective until either modified by new serial attributes or until the end of the row. A serial attribute is represented as a space (the space character itself however is not used for this purpose). The attributes are still active, e.g. overline and underline will be visible. The default settings at the start of a row are: * Foreground colour = 0, foreground colour switch = 0 (bank 0) * Background colour = 8 18.3.1 PARALLEL CHARACTER CODING
* Background colour duration = 0 * End of Row = 0. The coding is done in 12-bit words. The codes are stored sequentially in the display memory.
Table 54 Parallel character coding BITS 0 to 7 8 to 10 11 18.3.2 8-bit character code 3 bits for 8 foreground colours Mode bit: a logic 0 = parallel code SERIAL CHARACTER CODING DESCRIPTION
Table 55 Serial character coding SERIAL MODE 1 BITS 0 to 3 4 5 6 7 SERIAL MODE 0 (`SET AT') CHAR. POSITION = 1 (`SET AT') CHAR. POSITION >1 (`SET AFTER') 4 bits for 16 background colours 4 bits for 16 background colours 0 = Underline off 1 = Underline on 0 = Overline off 1 = Overline on Display mode: 0 = Superimpose; 1 = Boxing 0 = Flash off 1 = Flash on 0 = Italics off 1 = Italics on 0 = Fringing off 1 = Fringing on Switch for Serial coding Mode 0 and 1: 0 = Mode 0 Mode bit: 1 = Serial code Horizontal Size: 0 = normal; 1 = x2 Vertical Size: 0 = normal; 1 = x2 Display mode: 0 = Superimpose; 1 = Boxing Foreground colour switch 0 = Bank 0 (colours 0 to 7) 1 = Bank 1 (colours 8 to 15) Background colour duration: 0 = stop BGC 1 = set BGC to end of row End of Row 0 = Continue Row; 1 = End Row Switch for Serial coding Mode 0 and 1: 1 = Mode 1 Mode bit: 1 = Serial code 4 bits for 16 background colours 0 = Underline off 1 = Underline on 0 = Overline off 1 = Overline on Display mode: 0 = Superimpose; 1 = Boxing Foreground colour switch 0 = Bank 0 (colours 0 to 7) 1 = Bank 1 (colours 8 to 15) Background colour duration (set at): 0 = stop BGC 1 = set BGC to end of row End of Row (set at): 0 = Continue Row; 1 = End Row Switch for Serial coding Mode 0 and 1: 1 = Mode 1 Mode bit: 1 = Serial code
8
9 10 11
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.4 Screen controls 18.4.3 FRINGING COLOUR
P8xCx70 family
A number of 8-bit registers are provided which are used to select various parameters for the whole screen. 18.4.1 DISPLAY MODES
The colour of the fringe is set by the FRC0 to FRC3 bits in the Fringing Control Register (see Section 18.9.4). Any one of 16 colours can be selected. Table 58 Fringing colour FRC<3-0> FRINGING COLOUR 3 0 1 18.4.4 2 0 1 1 0 1 0 0 1 Colour 0 Colour 15
When superimpose or boxing are set, the resulting display depends on the setting of the screen display mode bits. The mode is selected by the MOD0 and MOD1 bits of the Display Control Register (see Section 18.9.1). * Video mode: disables all display activities and sets the RGB to true black and FBL to video. * Full Text mode: displays screen colour at all locations not covered by character foreground or background colour. The box attribute has no effect. * Mixed Screen mode: displays screen colour at all locations not covered by character foreground or, within boxed areas, background colour. * Mixed Video mode: displays video at all locations not covered by character foreground or within boxed areas, background colour. Table 56 Selection of screen display modes MOD1 0 0 1 1 18.4.2 MOD0 0 1 0 1 FRINGING CONTROLS DISPLAY MODE Video mode Full Text mode Mixed Screen mode Mixed Video mode
SCREEN COLOUR
The screen colour can be any one of 16 colours.The colour is selected using the SRC0 to SRC3 bits in the Display Control Register (see Section 18.9.1).The screen colour covers the full video width, as described in Section 18.7.1. It is visible when the Text mode is set and no foreground or background pixels are being displayed (see Section 18.4.1). Table 59 Selection of the screen colour SRC<3-0> SCREEN COLOUR 3 0 1 2 0 1 1 0 1 0 0 1 Colour 0 Colour 15
18.4.2.1
Fringing direction
18.4.5
FLASH FREQUENCY
Fringing can be set to work in any direction (N, S, E and W). The direction is selected by setting one of the four FRDx bits in the Fringing Control Register (see Section 18.9.4). Where x = N, S, E or W and N = North, S = South etc. Table 57 Selection of Fringing direction FRDx 0 1 FRINGING DIRECTION off on
The flash frequency is set by the FLF bit in the Display Control Register; (see Section 18.9.1). Table 60 Selection of the flash frequency FLF 0 1 FLASH FREQUENCY approximately 1 Hz with a 50% active ratio approximately 2 Hz with a 50% active ratio
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.5 Text display controls
P8xCx70 family
These controls are used for defining the display areas. Two types of areas are possible. One area is static and controlled via the main row counter, while the other is dynamic and can be soft scrolled. The areas cannot cross each other. Only one soft scroll area is possible. A scroll map is provided which is addressed by the display row and contains the address of the data in the memory that is to be displayed. A bit is also provided to enable the text display, outside of the scroll area. Outside the defined scroll area, the scroll map is addressed by the main row counter. Within the visible soft scroll area, the scroll map is addressed by the scroll row counter. The text display enable bit within this area is ignored. The number of rows that can be scrolled through can be set by defining the start row (scroll map value) and end row. The defined number of rows should be at least one more than the visible scroll area height. The height of the visible area is defined as a number of rows. The position of the scroll area is defined as an offset in number of rows from the start of the text area. The values programmed into the registers must ensure a sensible display. the following should be noted: * If values are programmed that cause the display to go beyond the vertical sync signal, the display will stop and react as if finished * If the visible scroll area is made larger than the number of rows allocated to the scroll function, then they will wrap around and be repeated * If the defined range of rows for scrolling is greater than the scroll area, these rows should not be used for other display purposes. 18.5.1 SOFT SCROLL ACTION
At the count 0, the scroll row counter is incremented automatically and the line-scan counter is set to 12 again. This pushes the top row to the bottom. This row must be cleared by the core during the fly-back period. If the number of rows allocated to the scroll counter is larger than the defined visible scroll area, this allows parts of rows at the top and bottom to be displayed during the scroll function. Only screens which contain single height rows or only double height rows can be scrolled.
18.5.1.1
Soft scroll enable
The soft scroll function is started by writing a logic 1 to the SCRL bit in the Read Only Status Register (see Section 18.9.9). This bit will be cleared when the scrolling of one row is completed. A hard scrolling action can also be performed when writing a logic 0 to the SCRL bit in the Write Only Status Register. If a logic 0 is written to this bit, the display in the scroll area is subsequently shifted up by one row. Table 61 Soft scroll enable SCRL 0 1 SOFT SCROLL Activates hard scroll, shifts display in one row increment, stops soft scroll. Start scrolling function.
18.5.1.2
Soft scroll area enable
The SCON bit in the Status Register controls whether a scroll area is active or not. The default value is no scroll area enabled, and the display is controlled only by the scroll map entries. When this bit is set to a logic 1 the scroll area is activated and the values contained in the SSACR, SRRR and STA registers take effect. Table 62 Soft scroll area enable SCON 0 1 SOFT SCROLL AREA no scroll area enabled scroll area enabled
The soft scrolling function is done by modifying the start count of the row scan-line count of the first scroll row. This is decremented once per frame automatically thus providing the effect of the top row disappearing while the bottom row is appearing.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.5.1.3 Top display row select 18.5.1.5
P8xCx70 family
Scroll rows range selection
The top display row of the scroll area is set using the SSP0 to SSP3 bits in the Soft Scroll Area Control Register (see Section 18.9.6). Table 63 Soft scroll area position value SSP<3-0> DISPLAY AREA POSITION 3 0 1 2 0 1 1 0 1 0 0 1 Row 0 Row 15
The scroll rows range is set in the Scroll Rows Range Register (see Section 18.9.7). Setting this register initialises the scroll row counter so that the first (top) row is the Start Scroll Row Number. By redefining the contents of this register a hard scrolling can also be achieved. If a new start scroll row number is loaded during a soft scroll action, then this value will be taken as the new start value after the scrolling action has been completed. Table 65 Start scroll row number STS<3-0> 3 2 0 1 1 0 1 0 0 1 START SCROLL ROW NUMBER Row 0 Row 15
18.5.1.4
Visible scroll area height selection
0 1
The visible scroll area height is set using the SSH0 to SSH3 bits in the Soft Scroll Area Control Register (see Section 18.9.6). Table 64 Soft scroll area height value SSH<3-0> DISPLAY AREA HEIGHT 3 0 1 2 0 1 1 0 1 0 0 1 1 Row 16 Rows
Table 66 Stop scroll row number SPS<3-0> 3 0 1 2 0 1 1 0 1 0 0 1 STOP SCROLL ROW NUMBER Row 0 Row 15
handbook, full pagewidth
scroll area position pointer (SSP3 to SSP0 e.g. 6) visible area height (SSH3 to SSH0 e.g. 4)
ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
usable for OSD display should not be used for OSD display soft scrolling area start row (STR3 to STR0 e.g. 3) stop row (SPR3 to SPR0 e.g. 11) should not be used for OSD display usable for OSD display
MGL148
Fig.17 Soft scroll area.
1999 Jun 11
46
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.5.2 SCROLL MAP
P8xCx70 family
The scroll map allows a flexible allocation of data in the memory, to individual rows. Sixteen 12-bit words are provided in the display memory for this purpose. The bit allocation is shown in Table 67. The scroll map memory is located in the first 16 words in the display memory (data byte addresses 8000H to 801FH) as shown in Fig.18. Table 67 Scroll map word format BIT 11 10 9 to 0 Reserved, should be set to a logic 0. Pointer to row data. DESCRIPTION Text display enable, valid outside soft scroll area. A logic 0 = disable; a logic 1 = enable.
handbook, full pagewidth
Display memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Text area display possible un-usable for OSD display soft Scrolling display possible
ROW 0 1 2 3 4 10 11 3 4 9 10 11 12 13 14 15
Row counter 0 to 15 valid
Scroll Map entries
available rows for scrolling
Enable bit = 0
Scroll counter 3 to 11 valid
un-usable for OSD display
Row counter 0 to 15 valid
display possible
MGK549
display data
Fig.18 Scroll map and data pointers.
1999 Jun 11
47
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.6 Memory mapping
P8xCx70 family
All registers and RAM in the display section are mapped into the upper 32-kbyte external RAM range of the 80C51 core. When writing to the display section, memory units (CLUT and the Display RAM) have wider formats than 8-bits. Two bytes are written for each word, the first byte (even addresses), addresses the lower 8-bits; the lower nibble of the second byte (odd addresses), addresses the upper 4-bits. 18.6.1 ACCESSING MEMORY
The memories can be accessed by the microprocessor as if it is external RAM.
processor byte n handbook, halfpage 7 0 processor byte n + 1 3 0
7
11 character data
0
MGL149
Fig.19 Byte mapping.
handbook, halfpage
microcontroller address 87FFH registers (16 bytes) 87F0H
internal RAM address F registers 0
CLUT (32 bytes)
871FH CLUT RAM 8700H
F 0
display data 2 bytes/ character scroll map
845FH 8020H 801FH 8000H
22FH display data RAM (1120 bytes) 000H
MGL152
Fig.20 Memory and register mapping.
1999 Jun 11
48
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.7 Display positioning
P8xCx70 family
The positioning of the display is relative to the vertical and horizontal sync pulses. The display consists of the screen colour covering the whole screen and the text area that is placed within the visible screen area. The screen colour extends over a large vertical and horizontal range so that no offset is needed. The text area offset in both directions is relative to the vertical and horizontal sync pulses.
handbook, full pagewidth
horizontal sync screen colour offset = 8 s 6 lines offset text vertical offset SCREEN COLOUR AREA horizontal sync delay TEXT AREA
vertical sync
0.25 character offset
text area start text area end 56 s
MGL150
Fig.21 Display area positioning.
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.7.1 SCREEN COLOUR DISPLAY AREA Table 71 Text area fine offset HOP1 0 0 1 1 HOP0 0 1 0 1
P8xCx70 family
The screen colour display area starts with a fixed offset of 8 s from the leading edge of the horizontal sync pulse in the horizontal direction. A vertical offset is not necessary. Table 68 Screen colour display area POSITION Horizontal Vertical 525-LINE Start at 8 s after leading edge of HSYNC for 56 s. Line 6, Field 1 (269, Field 2) to leading edge of vertical sync. 5 18.7.2 TEXT DISPLAY AREA 0 DESCRIPTION Up to 48 full sized characters per row. Start position setting from 3 to 64 characters from the leading edge of HSYNC. Fine adjustment in quarter characters. 208 lines (nominal 38 to 245). Start position setting from leading edge of vertical sync, legal values are 4 to 64 lines. 1 Table 69 Text display area POSITION Horizontal
TEXT POSITION HORIZONTAL FINE OFFSET 0 quarters 1 quarter 2 quarters 3 quarters
Table 72 Text vertical position VOL<5-0> 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 TEXT AREA VERTICAL LINE OFFSET 0 lines 63 lines
Vertical
The width of the text area is defined by setting the end character value (1 to 64 characters). This number determines where the background colour will end if set to extend to the end of the row. It will also terminate the character fetch process thus eliminating the necessity of a row end attribute. This entails however writing to all positions. The text area end is set by the TAE0 to TAE5 bits in the Text Area End Register (see Section 18.9.5). The width is the difference between the horizontal offset and the end value and is always as a number of full width characters (0 to 48 valid range). The quarter character offset in the Text Horizontal Position Register is also valid for the end position. Table 73 Text area end TAE<5-0> 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 TEXT AREA END FULL CHARACTERS 1 character 64 characters
The text area can be defined to start with an offset in both the horizontal and vertical direction. The horizontal offset is set in the Text Horizontal Position Register (see Section 18.9.3). The offset is in full width characters (1 to 64 characters) and quarter characters for fine setting (0 to 3 quarters). The vertical offset is set in the Text Vertical Position Register (see Section 18.9.2). The offset is done in number of lines (0 to 63). Table 70 Text area start offset TAS<5-0>(1) 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 1 TEXT POSITION HORIZONTAL TEXT AREA START 0 characters 63 characters
Note 1. The values `000000' to `000011' will result in a corrupted offset.
1999 Jun 11
50
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.8 18.8.1 General controls POLARITY OF HSYNC AND VSYNC INPUT SIGNALS
P8xCx70 family
These VSYNC pulses are gated (AND gate) with a line frequency signal which has a duty cycle of 50 : 50 (H50). The output signal is the frame reset pulse. The rising edge of the H50 signal is generated from the HSYNC pulse. The falling edge is generated via a comparison between the fixed value of half of the nominal number of 768 pixels per line (comparator value: 384 pixels) and the value of a pixel counter. If the VSYNC of one field occurs shortly after the falling edge of H50 and the line period has more than the nominal number of 768 pixels per line, it is possible that both VSYNC pulses occur during the low period of H50. The result is that no frame reset pulse is generated. In the case of a VSYNC pulse occurring shortly after the rising edge of H50 and less than the nominal number of 768 pixels per line it is possible that every VSYNC pulse will generate a frame reset pulse. To prevent this happening the position of H50 is adjustable in increments of 12 clock cycles. The adjustment value is selected using the Odd/Even Align Register.
The horizontal and vertical input sync signals can be inverted by setting the HPOL and VPOL bits in the Text Vertical Position Register (see Section 18.9.2). Table 74 Sync signal polarity HPOL 0 1 18.8.2 VPOL 0 1 SYNC SIGNAL POLARITY input polarity input inverted polarity
FRAME RESET GENERATION
Normally, VSYNC of the first field occurs during the first half line period and Vsync of the second field occurs during the second half period of a scan-line. In this case it is very easy to generate a frame reset signal. The VSYNC pulse is generated by sampling and rising edge detection.
handbook, Field 1 full pagewidth
Hsync
Vsync_In Vsync (sampled) H50 Frame reset
Field 2 Hsync
Vsync_In Vsync (sampled) H50 Frame reset
MGL151
Fig.22 Frame reset timing.
1999 Jun 11
51
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.9 Register descriptions
P8xCx70 family
All registers are read/writeable. When the registers are read a value will be returned that will correspond to the written data. There is one exception; when the Status Register is read, status information will be returned. 18.9.1 DISPLAY CONTROL REGISTER (DCR)
Table 75 Display Control Register (address 87F0H) 7 SRC3 6 SRC2 5 SRC1 4 SRC0 3 FLF 2 MSH 1 MOD1 B0 MOD0
Table 76 Description of DCR bits BIT 7 6 5 4 3 2 1 0 18.9.2 SYMBOL SCR3 SCR2 SCR1 SCR0 FLF MSH MOD1 MOD0 Flash frequency. The state of this bit determines the flash frequency of the screen. A frequency of 1 or 2 Hz can be selected; see Table 60. Meshing. If MSH = 1, meshing is selected. See Section 18.2.12. Display modes. These 2 bits select one of the four display modes: Video mode, Full Text mode, Mixed Screen mode and Mixed Video mode; see Table 56. DESCRIPTION Screen colour. These 4 bits select the screen colour; one of 16 colours may be selected; see Table 59.
TEXT VERTICAL POSITION REGISTER (TVPR)
Table 77 Text Vertical Position Register (address 87F1H) 7 VPOL 6 HPOL 5 VOL5 4 VOL4 3 VOL3 VOL2 1 VOL1 0 VOL0
Table 78 Description of TVPR bits BIT 7 6 5 4 3 2 1 0 SYMBOL VPOL HPOL VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 DESCRIPTION Vertical sync polarity. The state of this bit determines whether the vertical sync input is inverted or not; see Table 74. Horizontal sync polarity. The state of this bit determines whether the horizontal sync input is inverted or not; see Table 74. Vertical offset. These 6 bits select the number of lines that the text area is offset vertically; see Table 72.
1999 Jun 11
52
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.9.3 TEXT HORIZONTAL POSITION REGISTER (THPR)
P8xCx70 family
Table 79 Text Horizontal Position Register (address 87F2H) 7 HOP1 6 HOP0 5 TAS5 4 TAS4 3 TAS3 2 TAS2 1 TAS1 0 TAS0
Table 80 Description of THPR bits BIT 7 6 5 4 3 2 1 0 18.9.4 SYMBOL HOP1 HOP0 TAS5 TAS4 TAS3 TAS2 TAS1 TAS0 FRINGING CONTROL REGISTER (FCR) DESCRIPTION Fine horizontal offset. These 2 bits select a fine offset, ranging from 0 to 3 quarter characters; see Table 71. Text area start. These 6 bits select an offset of 0 to 63 full-width characters; see Table 70.
Table 81 Fringing Control Register (address 87F3H) 7 FRC3 6 FRC2 5 FRC1 4 FRC0 3 FRDN 2 FRDE 1 FRDS 0 FRDW
Table 82 Description of FCR bits BIT 7 6 5 4 3 2 1 0 SYMBOL FRC3 FRC2 FRC1 FRC0 FRDN FRDE FRDS FRDW Fringing directions. The fringing direction is selected by setting one of these bits to a logic 1. For example, when FRDN = 1, the fringing direction is North. See Table 57. DESCRIPTION Fringing colour. These 4 bits select the fringing colour. One of 16 colours can be specified; see Table 58.
1999 Jun 11
53
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.9.5 TEXT AREA END REGISTER (TAER)
P8xCx70 family
Table 83 Text Area End Register (address 87F4H) 7 - 6 - 5 TAE5 4 TAE4 3 TAE3 2 TAE2 1 TAE1 0 TAE0
Table 84 Description of TAER bits BIT 7 6 5 4 3 2 1 0 18.9.6 SYMBOL - - TAE5 TAE4 TAE3 TAE2 TAE1 TAE0 SOFT SCROLL AREA CONTROL REGISTER (SSACR) Text area end. These 6 bits assist in defining the width of the text area. The actual text area width is the difference between the horizontal offset and the value specified by these 6 bits; see Table 73. These 2 bits are reserved. DESCRIPTION
Table 85 Soft Scroll Area Control Register (address 87F5H) 7 SSH3 6 SSH2 5 SSH1 4 SSH0 SSP3 2 SSP2 1 SSP1 0 SSP0
Table 86 Description of SSACR bits BIT 7 6 5 4 3 2 1 0 SYMBOL SSH3 SSH2 SSH1 SSH0 SSP3 SSP2 SSP1 SSP0 Soft scroll area position. These 4 bits specify the top display row of the soft scroll area. One of 16 rows may be specified; see Table 63. DESCRIPTION Soft scroll area height. These 4 bits determine the visible scroll area height. One of 16 rows may be specified; see Table 64.
1999 Jun 11
54
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.9.7 SCROLL ROWS RANGE REGISTER (SRRR)
P8xCx70 family
Table 87 Scroll Rows Range Register (address 87F6H) 7 SPS3 6 SPS2 5 SPS1 4 SPS0 3 STS3 2 STS2 1 STS1 0 STS0
Table 88 Description of SRRR bits BIT 7 6 5 4 3 2 1 0 18.9.8 SYMBOL SPS3 SPS2 SPS1 SPS0 STS3 STS2 STS1 STS0 RGB BRIGHTNESS REGISTER (BR) Start scroll row. These 4 bits select the row number at which scrolling will begin. One of 16 rows can be specified; see Table 65. DESCRIPTION Stop scroll row. These 4 bits select the row number at which scrolling will stop. One of 16 rows can be specified; see Table 66.
Table 89 RGB Brightness Register (address 87F7H) 7 FBPOL 6 - 5 - 4 - 3 BRI3 2 BRI2 1 BRI1 0 BRI0
Table 90 Description of BR bits BIT 7 6 5 4 3 2 1 0 SYMBOL FBPOL - - - BRI3 BRI2 BRI1 BRI0 Brightness value. These 4 bits select the brightness value of the RGB output voltages. One of 16 brightness values can be selected; see Table 52. DESCRIPTION Fast Blanking polarity. The state of this bit determines whether the polarity of the Fast Blanking signal (FBL) is inverted or not; see Table 51. These 3 bits are reserved.
1999 Jun 11
55
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.9.9 STATUS REGISTER (SR)
P8xCx70 family
A status register is provided that holds information that the processor can use to regulate the way data is written into the display unit. The register is split into a read only and write only register. Both use the same address. Table 91 Status Register (address 87F8H); read only 7 BUSY 6 - 5 FIELD 4 SCRL 3 SCR3 2 SCR2 1 SCR1 0 SCR0
Table 92 Description of SR bits BIT 7 SYMBOL BUSY DESCRIPTION Character display active or vertical sync. If BUSY = 0, this indicates that the processor can access the display unit without causing effects on the screen. The lead time is 4 ms, this is implemented to allow the microcontroller to finish the current access to the display memory. Two modes are provided to switch between the text horizontal blank area or vertical blank area. Random information. 1st or 2nd Field of vertical frame. Scroll busy. If SCRL = 1, this bit indicates that the scroll function is in progress. When this bit is set, the automatic scroll function is started. It is automatically cleared on completion. If forced to a logic 0, the scroll function will be terminated as if all lines were scrolled. Subsequent logic 0 writes will cause the scroll row to increment by one. First scroll row select. The value specified by these 4 bits selects the actual row that is the first one to be displayed in the scroll area. This value is modified by the automatic scroll function.
6 5 4
- FIELD SCRL
3 2 1 0
SCR3 SCR2 SCR1 SCR0
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
Table 93 7 - Status Register (address 87F8H); write only 6 H/V 5 SCON 4 SCRL 3 - 2 -
P8xCx70 family
1 -
0 -
Table 94 Description of SR bits BIT 7 6 5 4 SYMBOL - H/V SCON SCRL DESCRIPTION This bit is not used and causes no action. Busy signal switch horizontal/vertical. If H/V = 0, horizontal blank area selected. If H/V = 1, vertical blank area selected. Scroll area enabled. If SCON = 1, then the scroll area is enabled. See Section 18.5.1.2. Start scroll. If SCRL = 1, this bit indicates that the scroll function is in progress. When this bit is set, the automatic scroll function is started. It is automatically cleared on completion. If forced to a logic 0, the scroll function will be terminated as if all lines were scrolled. Subsequent logic 0 writes will cause the scroll row to increment by one. These 4 bits are not used and cause no action.
3 2 1 0
- - - -
18.9.10 HSYNC DELAY REGISTER (HSDR) Table 95 HSYNC Delay Register (address 87FCH) 7 - 6 HSD6 5 HSD5 4 HSD4 3 HSD3 2 HSD2 1 HSD1 0 HSD0
Table 96 Description of HSDR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - HSD6 HSD5 HSD4 HSD3 HSD2 HSD1 HSD0 reserved HSYNC delay. These 7 bits allow the position of the HSYNC pulse to be changed in increments of full width characters. A delay of 0 to 63 full width characters can be selected. DESCRIPTION
1999 Jun 11
57
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.9.11 ODD/EVEN ALIGN REGISTER (OEAR)
P8xCx70 family
Table 97 Odd/Even Align Register (87FDH) 7 - 6 OEA6 5 OEA5 4 OEA4 3 OEA3 2 OEA2 1 OEA1 0 OEA0
Table 98 Description of OEAR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - OEA6 OEA5 OEA4 OEA3 OEA2 OEA1 OEA0 reserved H50 delay. These 7 bits allow the position of the H50 pulse to be changed in increments of 12 clock pulses. DESCRIPTION
1999 Jun 11
58
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.9.12 CONFIGURATION REGISTER (CONFR)
P8xCx70 family
The Configuration Register is provided for special purposes and to program the delay between the RGB and FBL output. Table 99 Configuration Register (address 87FFH) 7 CC 6 PLUS 5 ADJ 4 MIN 3 - 2 - 1 - 0 -
Table 100 Description of CONFR bits BIT 7 SYMBOL CC DESCRIPTION Closed Caption mode. The state of this bit selects the OSD mode or the CC mode. If CC = 0, then the OSD mode is selected; this is also the default setting. If CC = 1, then the CC mode is selected. In the CC mode the underline is suppressed during the display of a serial attribute. The display is then according to the CC specification. FBL delay select. These 3 bits define the timing of the FBL signal; see Table 101.
6 5 4 3 2 1 0
PLUS ADJ MIN - - - -
Reserved, set to logic 0. These 3 bits are used for test purposes only and should be set to logic 0s for normal operation.
Table 101 FBL delay adjustment PLUS 0 0 0 1 X ADJ 0 0 1 0 X MIN 0 1 0 0 X FBL TIMING FBL switched to video, not active. FBL active one pixel early to RGB. FBL synchronous with RGB (typical setting). FBL active one pixel delayed to RGB. All other combinations are allowed and will have the effect that the above settings are functionally ORed, e.g. `111' will result in a 3 pixel wide FBL pulse when one single pixel is displayed.
1999 Jun 11
59
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.10 Character font format The character font is a 12 (horizontal) x 13 (vertical) matrix. The ROM contents have two extra lines in each field to facilitate the fringing function when groups of characters are used to build symbols. A table with 128 characters, two columns of special characters (32) and a column for proportional spaced characters (16) is shown in Fig.27. The ROM size is 176 characters x 12 x 16 = 33792 bits (4224 bytes, 2816 x 12-bit words). 18.10.1 CHARACTER ROM FORMAT The character addressing scheme is dependent on what type of character is accessed. Therefore, the ROM format for the different columns changes respectively. The ROM format is 16 locations in words of 12 bits, where the MSB (bit 11) of the ROM word is the left most pixel of a character displayed. The lines 0 and 14 are used for fringing of clustered characters (single images using more than one character) over row boundaries. Lines 1 to 13 contain the font of the character and line 15 is not used.
P8xCx70 family
The proportional spaced characters use only bits 11 to 6 for display. Bits 5 to 0 are defined by repeating the information held in bits 11 to 6 shifted up one line. The ROM definition for these characters is shown in Fig.24. Proportional characters can be displayed in column A only. The ROM format for the special characters uses two subsequent character ROM locations. The character definition will always start with an even character. This location holds the information for bit Plane 0 the next location (odd) contains the bit Plane 1. No shadowing is supported when using these characters. The bit combinations of Plane 0 and Plane 1 define which colour is displayed for a certain pixel. A detailed description on how these characters are displayed is found in Section 18.2.16. The ROM format for each plane is defined as stated for the normal characters, except that the data on the fringing lines is ignored.
handbook, halfpage
top left pixel line number HEX MSB 440 0 003 1 00C 2 030 3 0C0 4 300 5 C00 6 C00 7 300 8 0C0 9 030 10 00C 11 003 12 000 13 198 14 000 15
line 13 from character above LSB fringing top line
handbook, halfpage HEX line
line 0 from character below
bottom line fringing line not used bottom right pixel
MGL153
number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
value 000 000 00C 300 00C 30C 30C 30C 30C 30C 306 180 000 000 000 000
11 (MSB)
fringe(1)
65
0 (LSB)
fringe(3) not used
fringe(2) not used
MGL154
(1) Line 13 from character above. (2) Line repeated from line 14 (bits 11 to 6). (3) Line 1 from character below.
Fig.23 Character ROM format columns 0 to 7.
Fig.24 Proportional character ROM format column A.
1999 Jun 11
60
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
18.10.2 ROM ADDRESSING
P8xCx70 family
Figures 25 and 26 illustrate the addressing schemes used to access the different character formats. Figure 25 shows the ROM organization of the normal and proportional spaced characters and Fig.26 shows the ROM organization of the special characters. The address calculation in on the basis of word access. If the CPU accesses the ROM, a two byte access must be performed to capture the data, the data format is according to the definition in Fig.19.
handbook, halfpage
12 bits
handbook, halfpage 12 bits
word address = C000H
word address = C000H
word address = (X x 16) + C000H character X word address = [(X + 1) x 16] + C000H character X + 1 X = 0, 1, 2, 3,....
character X plane 0 character X plane 1
word address = (X x 16) + C000H word address = [(X + 1) x 16] + C000H X = 0, 2, 4,....
MGL155
MGL156
Fig.25 Character ROM organisation.
Fig.26 Character ROM organization for columns 8 and 9.
handbook, full pagewidth
Character code columns (bits 4 to 7) 0 1 (R) 2 SP ! 3 0 1 2 3 4 5 6 7 8 9 4 @ A B C D E F G H I J K L M N O 5 P Q R S T U V W X Y Z [ e ] I o 6 u a b c d e f g h i j k l m n o N n n
MGR275
7 p q r s t u v w x y z c
8 (B)
9 (C)
A (D)
0 1 2 Character code rows (bits 0 to 3) 3 4 5 6 7 8 9 A B C D E F
1/2 TM a
"
# $ % &
( ) a
_
e a e i o u
+
,
-
.
/
: ; < = >
?
Fig.27 Character table.
1999 Jun 11
61
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
19 MEMORY DATA BIT ALLOCATION Table 102 Register map bit allocation ADDR. 87F0H 87F1H 87F2H 87F3H 87F4H 87F5H 87F6H 87F7H 87F8H 87F8H 87FCH 87FDH 87FEH 87FFH REGISTER NAME Display Control Text Vertical Position Text Horizontal Position Fringing Control Text Area End Scroll Area Scroll Range RGB Brightness Status (read) Status (write) HSYNC Delay Odd/Even Align Reserved Configuration Register 7 SRC3 VPOL HOP1 FRC3 - SSH3 SPS3 FBPOL BUSY - - - - CC 6 SRC2 HPOL HOP0 FRC2 - SSH2 SPS2 - - H/V HSD6 OEA6 - PLUS 5 SRC1 VOL5 TAS5 FRC1 TAE5 SSH1 SPS1 - FIELD SCON HSD5 OEA5 - ADJ 4 SRC0 VOL4 TAS4 FRC0 TAE4 SSH0 SPS0 - SCRL SCRL HSD4 OEA4 - MIN 3 FLF VOL3 TAS3 FRDN TAE3 SSP3 STS3 BRI3 SCR3 - HSD3 OEA3 - -
P8xCx70 family
2 MSH VOL2 TAS2 FRDE TAE2 SSP2 STS2 BRI2 SCR2 - HSD2 OEA2 - -
1 MOD1 VOL1 TAS1 FRDS TAE1 SSP1 STS1 BRI1 SCR1 - HSD1 OEA1 - -
0 MOD0 VOL0 TAS0 FRDW TAE0 SSP0 STS0 BRI0 SCR0 - HSD0 OEA0 - -
Table 103 Memory data/bit allocation ODD BYTE BITS 3 TO 0 B11 - B10 B9 B8 B7 B6 B5 EVEN BYTE BITS 7 TO 0 B4 B3 B2 B1 B0
Valid for byte address 8000H to 801FH in display memory: Scroll map En. ptr9 ptr8 ptr7 ptr6 ptr5 ptr4 ptr3 ptr2 ptr1 ptr0
Valid for byte address 8020H to 8460H in display memory: Display page, first column position 1 = ser. 1 = at eof bgc for3 box vert. sync hor.sync back3 back2 back1 back0
Valid for byte address 8020H to 8460H in display memory: Display page, all columns 0 = par. for3 1 = ser. 0 = at for2 for1 chr7 flash chr6 box chr5 overline chr4 chr3 chr2 back2 chr1 back1 chr0 back0 fringing italic underline back3
Valid for byte address 8020H to 8460H in display memory: Display page, all columns except first position 1 = ser. 1 = after eof red3 19.1 19.1.1 red2 Interfaces RGB AND BLANKING OUTPUT red1 bgc red0 for3 green3 box green2 overline green1 underline back3 green0 blue3 back2 blue2 back1 blue1 back0 blue0 Valid for byte address 8700H to 871FH: CLUT
The RGB outputs are analog signals derived from a DAC. The output impedance depends on the switched value, but is low enough to drive the colour decoder. The polarity and the delay between RGB outputs and the blanking output is programmable. The default setting is active HIGH (RGB on).
1999 Jun 11
62
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
20 PROGRAMMER The P87Cx70 OTP contains two EPROM modules, one 64-kbyte system EPROM and one 8-kbyte character EPROM. Users can program or verify both system and character EPROM with a PC using Intel HEX format. 20.1 EPROM Interface
P8xCx70 family
The main 64-kbyte OTP operation is the core function of programming. The customer can program the software using an EPROM writer. Extra row programming is similar to test ROM in mask ROM and can be used to store production IDs, testing patterns etc. The select two bytes programming operation is used to speed up the programming of the checker board. The Programming configuration is shown in Fig.28. 20.2.2 VERIFY MODE
Port 0 and Port 2 are used as the 16-bit address bus; Port 0 for the higher address byte and Port 2 for the lower address byte. Port 3 is used as an 8-bit bidirectional data bus during programming and verify operations. For control signals, ALE/PROG is used as the write strobe (WE) and P1.0 is used as the output enable (OE). Pin 28 is the programming voltage (VPP) input and requires 12.75 V during the Programming mode and 5 V during the Verification mode. The required input on the RESET, PSEN and P1.0 to P1.4 pins is dependent upon the mode selected. Signal states for the three modes are specified in Table 104 and the timing characteristics of these signals are detailed in Section 20.5. 20.2 OTP application mode
The Verify mode performs two operations: Program verify and Extra row read. The program verify operation checks that the value programmed is correct. The Extra row read mode is similar to the Program verify mode and ensures that the extra row programming is correct. The Program verification configuration is shown in Fig.29. 20.3 Programming format for character EPROM
The character EPROM programming data format contains 12-bit OSD data for each character row; 4 bits from OSDH and 8 bits from OSDL. The encoding sequence is shown in Fig.30. The address range of the 8-kbyte character EPROM is from C000H to DFFFH. 20.4 Programming format for system EPROM
The OTP application mode consists of two major sub-modes: Programming mode and Verify mode. The pin assignment during OTP programming and verification operations is specified in Table 105. 20.2.1 PROGRAMMING MODE
The system EPROM format is the same as for normal EPROM and is programmed sequentially using Intel Hex format. The address range of the 64-kbyte system EPROM is from 0000H to FFFFH.
The Programming mode performs three operations: main 64-kbyte OTP, extra row programming and select two bytes programming. Table 104 OTP function table OPERATION MODE Programming Program verify 2-byte programming RESET 1 1 1 PSEN 0 0 0 ALE/WE LOW pulse H LOW pulse
EA/VPP VPP VDD VPP
P1.3 1 1 0
P1.2 1 1 0
P1.1 1 1 1
P1.0/OE H LOW pulse H
1999 Jun 11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
Table 105 Pin assignment during programming and verification operations SYMBOL P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 ALE/PROG VPP/EA RST PSEN PIN 1 2 3 4 5 6 7 8 9 10 11 12 30 21 20 19 18 17 16 15 14 45 46 47 48 49 50 51 52 29 28 43 27 SYSTEM EPROM A8 A9 A10 A11 A12 A13 A14 A15 OE OTP SEL0 OTP SEL1 OTP SEL2 (LOW) A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 WE VPP (HIGH) (LOW)
P8xCx70 family
OSD EPROM A8 A9 A10 A11 A12 (LOW) (HIGH) (HIGH) OE OTP SEL0 OTP SEL1 OTP SEL2 (HIGH) A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 WE VPP (HIGH) (LOW)
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
5V A7 to A0 1 L-pulse 1 1 1 1 1/0 P2.7 to P2.0 RESET ALE/PROG P1.3 P1.0 P1.1 P1.2 P1.4 VSS P3.7 to P3.0
MGR376
VDD
P0.7 to P0.0
A15 to A8
P87C770 (OTP)
VPP/EA
12.75 V
PSEN
0
D7 to D0
Fig.28 Programming configuration.
handbook, full pagewidth
5V A7 to A0 1 1 1 1 P1.0 0 1 1 1/0 P1.1 P1.2 P1.4 VSS P3.7 to P3.0
MGR377
P2.7 to P2.0 RESET ALE/PROG P1.3
VDD
P0.7 to P0.0
A15 to A8
P87C770 (OTP)
VPP/EA
5V
PSEN
0
D7 to D0
Fig.29 Program verification configuration.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
OSDH <3 to 0> 11 0 3 87
OSDL <7 to 0> 10
OSDL OSDH (HEX) (HEX) 00 03 83 C3 60 07 08 E8 08 07 60 C3 83 03 00 00 00 00 01 00 00 00 00 07 00 00 00 00 01 00 00 00
7
13 15 :10 C000 00 :10 C010 00 :10 CFFF 00
00 00 03 00 83 01 C3 00 60 00 07 00 08 00 E8 07 08 00 07 00 60 00 C3 00 83 01 03 00 00 00 00 00
MGR375
Fig.30 Data format of character EPROM.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
20.5 EPROM timing characteristics
P8xCx70 family
Table 106 EPROM programming timing SYMBOL tsu(A) th(A) tsu(OE) tsu(CE) tW(P) tsu(PV) th(WE) tsu(D) th(D) tW(OE) tACC(OE) tOZ address set-up time address hold time output enable set-up time chip enable set-up time program pulse width (typically 5 programming pulses) program voltage set-up time write enable hold time data set-up time data hold time output enable pulse width output enable access verify output to high-impedance verify PARAMETER MIN. 2 20 2 2 95 2 110 2 20 300 92 10 TYP. - - - - 100 - - - - - 122 - MAX. - - - - 105 - - - - - 183 - UNIT s ns s s s s ns s ns ns ns ns
handbook, full pagewidth
PROGRAMMING
tsu(PV)
VERIFY
12.75 V VPP/EA tW(P) WE (ALE/PROG) tsu(A) address (Ports 0 and 2) th(A) th(WE) 5V
address tsu(CE)
CE (internal signal) tsu(OE) OE (P10) tsu(D) data I/O (Port 3) th(D) tACC(OE) tOZ data out from EPROM
MGR374
tW(OE)
data in for EPROM
Fig.31 EPROM programming timing diagram.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, halfpage
A8 A9 A10 A11 A12 A13 A14 A15 P1.0/AFT0
1 2 3 4 5 6 7 8 9
52 D7 51 D6 50 D5 49 D4 48 D3 47 D2 46 D1 45 D0 44 VDDC 43 RESET 42 XI 41 XO 40 VSSD
P1.1/AFT1 10 P1.2/AFT2 11 P1.3/PWM0 12 VSSD 13
P8xC770
A7 14 A6 15 A5 16 A4 17 A3 18 A2 19 A1 20 A0 21 VSSA 22 CVBS 23 STN 24 BLK 25 IREF 26
MGR373
39 VDDP 38 VDDA 37 VSYNC 36 HSYNC 35 FB 34 R 33 G 32 B 31 REFH 30 P1.4 29 ALE/PROG 28 VPP/EA 27 PSEN
Fig.32 Programming pinning configuration.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
Table 107 Programming configuration pin descriptions SYMBOL P0.0 to P0.7 P1.0/AFT0 P1.1/AFT1 P1.2/AFT2 P1.3/PWM0 VSSD P2.7 to P2.0 VSSA CVBS STN BLK IREF PSEN VPP/EA PIN 1 to 8 9 10 11 12 13 14 to 21 22 23 24 25 26 27 28 I ALE/PROG P1.4 REFH B G R FB HSYNC VSYNC VDDA VDDP VSSD XO XI RESET VDDC P3.0 to P3.7 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 to 52 I/O I/O I O O O O I I - - I O I I - I/O I/O I/O I/O I/O I/O I/O - I/O - I I I I O address lines A8 to A15 Port line P1.0; alternative function as 4-bit AFT0 input Port line P1.1; alternative function as 4-bit AFT1 input Port line P1.2; alternative function as 4-bit AFT2 input DESCRIPTION
P8xCx70 family
Port line P1.3 (open-drain, bidirectional); alternative function as 7-bit PWM output digital ground address lines A7 to A0 analog ground composite video input Data Slicer decoupling capacitor input, connect to VSSA via a 100 nF capacitor. CVBS signal black level reference, connect to VSSA via a 100 nF capacitor. CVBS signal reference current input, connect to VSSA via a 27 k resistor. Program Store Enable (active LOW) is bonded out for testing purpose only. External Access (active LOW) is bonded out for testing purpose only; this pin is also used for the 12.75 V programming voltage supply in program/font OTP programming modes. Address Latch Enable is bonded out for testing purposes only; this pin is also used for programming pulses input in program/font OTP programming modes. Port line P1.4 (open-drain, bidirectional) Data Slicer reference high capacitor input, connect to VSSA via a 100 nF capacitor. CC/OSD Blue colour current output CC/OSD Green colour current output CC/OSD Red colour current output CC/OSD fast blanking output TV horizontal sync input (for OSD synchronization) TV vertical sync input (for OSD synchronization) 5 V analog power supply 5 V digital power supply digital ground system oscillator crystal output system oscillator crystal input reset input (active HIGH) 5 V digital power supply data I/O lines, D0 to D7
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
21 LIMITING VALUES SYMBOL VDD Vi Ptot Tstg Tamb Vesd PARAMETER supply voltage input voltage on any pin with respect to ground (VSS) total power dissipation storage temperature operation ambient temperature electrostatic protection HBM electrostatic protection MM 22 DC CHARACTERISTICS leakage < 1 A leakage < 1 A CONDITIONS MIN. -0.5 -0.5 - -55 -20 -2000 -250
P8xCx70 family
MAX. +7.0 VDD + 0.5 700 +125 +70 +2000 +250 V V
UNIT
mW C C V V
VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = -20 to +70 C. All voltages with respect to VSS, unless otherwise specified. SYMBOL Supply VDDC IDDC VDDP IDDP VDDA IDDA VIL VIH ILI VOL Port 2 outputs VOL LOW-level output voltage IOL = 3 mA IOL = 10 mA - - 0 0.7VDD IOL = 3 mA IOL = 10 mA - - - - - - - - 0.4 1 0.3VDD VDD 0.4 1 V V V V V V digital core supply voltage digital supply current peripheral supply voltage peripheral supply current analog supply voltage analog supply current LOW-level input voltage HIGH-level input voltage input leakage current LOW-level output voltage 4.5 - 4.5 - 4.5 - 0 0.7VDD -10 - 5.0 47 5.0 20 5.0 9 - - - - 5.5 - 5.5 - 5.5 - 0.3VDD VDD +10 0.4 V mA V mA V mA V V A V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ports 1, 2 and 3 inputs
VSS < VI < VDD IOL = 3 mA
Ports 1, 2 and 3 outputs (open-drain)
ALE, PSEN and EA inputs VIL VIH VOL LOW-level input voltage HIGH-level input voltage LOW-level output voltage
ALE, PSEN and EA outputs (open-drain)
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
SYMBOL PARAMETER CONDITIONS MIN. - - - 8.9 0 0 - 7 14 5 TYP.
P8xCx70 family
MAX.
UNIT
AFT inputs: P1.0/AFT0, P1.1/AFT1 and P1.2/AFT2 Vai Vae comparator analog input voltage conversion error range VSS P83C770 P87C770 -0.5 -0.7 - -12 -12 -12 P83C770; VO = 0.4 V P87C770; VO = 0.4 V VO = VDD - 0.4 V - - - VDD +0.5 +0.7 - +12 +12 +12 - - - V LSB LSB mA LSB LSB LSB mA mA mA
R, G and B outputs (4-bit DAC current source) IOH INL DNL FB output IOL IOH RESET VIL VIH Rrst LOW-level input voltage HIGH-level input voltage internal reset pull-down resistor LOW-level input voltage HIGH-level input voltage input leakage current input capacitance sync amplitude video input amplitude (peak-to-peak value) caption data amplitude source impedance input switching level of sync separator input impedance input capacitance external resistor to ground voltage on pin 0 0.7VDD 50 - - - 0.3VDD VDD 200 V V k LOW-level output source current HIGH-level output source current HIGH-level output source current integral non-linearity differential non-linearity matching RGB
HSYNC and VSYNC inputs VIL VIH ILI Cin CVBS input Vsync Vl(vid) Vldat Zsource Vin Zi Ci IREF input RIREF VIREF Power-on reset Vt trigger level 3.6 3.9 4.2 V - - 27 0.5VDD - - k V 0.1 0.7 0.25 1.8 2.5 - 0.3 1.0 0.35 2.15 5 - 0.6 1.4 0.49 250 2.5 - 10 V V V V k pF -0.3 3.15 - - - - - - 0.8 VDD + 0.5 10 5 V V A pF
VI = 0 to VDD
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
P8xCx70 family
handbook, full pagewidth
VDD (volts) 5
conversion error range <0.5 LSB
conversion error range <0.7 LSB
4
ideal
3
actual
2
1
0
1/16
3/16
5/16
7/16
9/16
11/16
13/16 14/16
15/16 16/16
MGR276
fraction of VDD
Fig.33 AFT conversion error range.
handbook, full pagewidth
ADC error (LSB) 0.7
0.5
0.3
0.1 0 1/16 3/16 5/16 7/16 9/16 11/16 13/16 14/16 fraction of VDD 15/16 16/16
MGR277
Fig.34 ADC error.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
23 AC CHARACTERISTICS
P8xCx70 family
VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = -20 to +70 C. All voltages with respect to VSS, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. - MAX. - UNIT
Ports 0, 1 and 3 outputs (open-drain) tf(o) output fall time CL = 35 pF; (slope control implemented) 30 ns
ALE, PSEN and EA outputs (slope control implemented) tr(o) tf(o) XI and XO fxtal TAFT(con) FB output tr(FB) tf(FB) FB rise time FB fall time CL = 35 pF - - - - - at power-on VDD: 0 5 V voltage spike VDD: 5 V Vt tW POR pulse width at power-on VDD: 0 5 V voltage spike VDD: 5 V Vt Note 1. Susceptibility for environment noise @ 1 VPP CVBS, 25 C;12 MHz. 4 4 - - - - - - - - - ns ns crystal frequency - - 12 - - MHz s output rise time output fall time CL = 40 pF CL = 40 pF - 30 - - - - ns ns
AFT inputs: P1.0/AFT0, P1.1/AFT1 and P1.2/AFT2 conversion time fxtal = 12 MHz 8
CVBS Closed Caption behaviour white noise (rms value) co-channel interface (peak-to-peak value) eye height Power-on reset Tr POR response time 5 5 10 10 - - - - s s s s 60 100 55 mV mVPP %
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
24 APPLICATION INFORMATION
P8xCx70 family
handbook, full pagewidth
P0.0/PWM8 P0.1/PWM7 P0.2/PWM6 P0.3/PWM5 P0.4/PWM4 P0.5/PWM3 P0.6/PWM2 P0.7/PWM1 P1.0/AFT0 P1.1/AFT1 P1.2/AFT2 P1.3/PWM0 VSSD GNDD P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 VSSA GNDA CVBS signal GNDA GNDA 100 nF 100 nF 100 nF CVBS STN BLK IREF 27 k GNDA
1 2 3 4 5 6 7 8 9 10 11 12 13
52 51 50 49 48 47 46 45 44 43 42 41 40
P3.7 P3.6 P3.5/SDA P3.4/SCL P3.3/T1 P3.2/INT0 P3.1/T0 P3.0/INT1 VDDC RESET XI XO VSSD VDDP VDDA VSYNC HSYNC FB R G B REFH P1.4 ALE/PROG VPP/EA PSEN 100 nF GNDA 10 k 5V 10 k 10 k 100 nF 47 F GNDA GNDD 12 MHz 22 pF 2.2 H 5V
22 pF GNDD
P8XC770
14 15 16 17 18 19 20 21 22 23 24 25 26
39 38 37 36 35 34 33 32 31 30 29 28 27
MGR919
5V
Fig.35 Application diagram.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
25 RELEASE LETTER OF ERRATA 25.1 Bugs with a software workaround 25.2
P8xCx70 family
Bugs with no workaround
* The soft scroll active bit and the top scroll row are not synchronized. Therefore, it is not possible to calculate from this bit and the top scroll row the current base row (the row which is displayed as the lowest one or which scrolls in). The top scroll row number is incremented immediately after the soft scroll function is finished but the soft scroll active bit remains set. The soft scroll active bit is cleared one field/frame later. A software workaround is implemented. * If the soft scroll function is to be stopped (write 0 x 20 to OSD Status Register) the soft scroll should stop immediately, but it stops at the end of the field/frame. After stopping the soft scroll function the soft scroll active bit should be cleared and the top scroll row number (lower 4 bit of the OSD Status Register) should be incremented by one. But sometimes the top scroll row number is incremented by two. Also in the stopped soft scroll the display sometimes jumps out of the defined scroll range. For example, the range is defined from row 0 to 5 and row 8 to 14 is displayed. A correction is possible after the next frame, which results in the stopped soft scroll (0.2 after soft scroll has been started a stop soft scroll is sent) to sometimes generate a display flicker. * Read/Write problem with access to Display Memory by the CPU. The error rate is 1/84000 (synchronized clock). The error is synchronous to the HSYNC with approximately 11 s delay after HSYNC. The automatically incremented DPTR didn't work correctly. A move command to the display memory (MOVX @DPTR,A) or (MOVX A, @DPTR) sometimes delivers a wrong result (e.g. an `A' should be written/read but a `B' is stored/read in/from the memory). A software workaround has been designed.
* The foreground colour of the first character behind a double size/width attribute is ignored. * During a double height row, if shadow is active, a north shadow appears above the last line of the row whether the underline is active or not. 25.3 Specification problems (unspecified)
* Soft scroll function cannot be stopped immediately (behaviour is not specified in the specification). If the decoder wants to terminate the soft scroll function, the soft scroll function stops one field/frame later. A restart is not possible before the scrolling has stopped. Therefore, a restart of the soft scroll function must be delayed by one field/frame. A software workaround is implemented. According to the CC specification the time between stop and start should be no more than 0.433 seconds. With the method as implemented the start command will be issued after 0.46 seconds. * The OSD does not allow the active edges of HSYNC and VSYNC to come at exactly the same moment * Soft scroll does not work, if a double height row is the top row of the scroll area. The specification has been changed to `the soft scroll function with double height rows is forbidden'.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
26 PACKAGE OUTLINE SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
P8xCx70 family
SOT247-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 wM (e 1) MH b 52 27
pin 1 index E
1
26
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
27 SOLDERING 27.1 Introduction to soldering through-hole mount packages
P8xCx70 family
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 27.3 Manual soldering
This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 27.2 Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. 27.4
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING WAVE suitable(1)
DBS, DIP, HDIP, SDIP, SIL Note
suitable
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
28 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
P8xCx70 family
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 29 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 30 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)
NOTES
P8xCx70 family
1999 Jun 11
79
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 65
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
275002/02/pp80
Date of release: 1999 Jun 11
Document order number:
9397 750 06084

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